📄 ascii.htm
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FTCPE_rma/ram_3_4: FTCPE port map (rma/ram_3_4,rma/ram_3_4_T,clk,'0','0');
rma/ram_3_4_T <= ((rma/ram_3_4 AND wr_en AND NOT di(4) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (NOT rma/ram_3_4 AND wr_en AND di(4) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
FTCPE_rma/ram_3_5: FTCPE port map (rma/ram_3_5,rma/ram_3_5_T,clk,'0','0');
rma/ram_3_5_T <= ((rma/ram_3_5 AND wr_en AND NOT di(5) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (NOT rma/ram_3_5 AND wr_en AND di(5) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
FTCPE_rma/ram_3_6: FTCPE port map (rma/ram_3_6,rma/ram_3_6_T,clk,'0','0');
rma/ram_3_6_T <= ((rma/ram_3_6 AND wr_en AND NOT di(6) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (NOT rma/ram_3_6 AND wr_en AND di(6) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
FTCPE_rma/ram_3_7: FTCPE port map (rma/ram_3_7,rma/ram_3_7_T,clk,'0','0');
rma/ram_3_7_T <= ((rma/ram_3_7 AND wr_en AND NOT di(7) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (NOT rma/ram_3_7 AND wr_en AND di(7) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
FTCPE_rma/ram_4_0: FTCPE port map (rma/ram_4_0,rma/ram_4_0_T,clk,'0','0');
rma/ram_4_0_T <= ((rma/ram_4_0 AND wr_en AND NOT di(0) AND NOT ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (NOT rma/ram_4_0 AND wr_en AND di(0) AND NOT ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
FTCPE_rma/ram_4_1: FTCPE port map (rma/ram_4_1,rma/ram_4_1_T,clk,'0','0');
rma/ram_4_1_T <= ((rma/ram_4_1 AND wr_en AND NOT di(1) AND NOT ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (NOT rma/ram_4_1 AND wr_en AND di(1) AND NOT ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
FTCPE_rma/ram_4_2: FTCPE port map (rma/ram_4_2,rma/ram_4_2_T,clk,'0','0');
rma/ram_4_2_T <= ((rma/ram_4_2 AND wr_en AND NOT di(2) AND NOT ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (NOT rma/ram_4_2 AND wr_en AND di(2) AND NOT ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
FTCPE_rma/ram_4_3: FTCPE port map (rma/ram_4_3,rma/ram_4_3_T,clk,'0','0');
rma/ram_4_3_T <= ((rma/ram_4_3 AND wr_en AND NOT di(3) AND NOT ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (NOT rma/ram_4_3 AND wr_en AND di(3) AND NOT ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
FTCPE_rma/ram_4_4: FTCPE port map (rma/ram_4_4,rma/ram_4_4_T,clk,'0','0');
rma/ram_4_4_T <= ((rma/ram_4_4 AND wr_en AND NOT di(4) AND NOT ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (NOT rma/ram_4_4 AND wr_en AND di(4) AND NOT ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
FTCPE_rma/ram_4_5: FTCPE port map (rma/ram_4_5,rma/ram_4_5_T,clk,'0','0');
rma/ram_4_5_T <= ((rma/ram_4_5 AND wr_en AND NOT di(5) AND NOT ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (NOT rma/ram_4_5 AND wr_en AND di(5) AND NOT ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
FTCPE_rma/ram_4_6: FTCPE port map (rma/ram_4_6,rma/ram_4_6_T,clk,'0','0');
rma/ram_4_6_T <= ((rma/ram_4_6 AND wr_en AND NOT di(6) AND NOT ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (NOT rma/ram_4_6 AND wr_en AND di(6) AND NOT ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
FTCPE_rma/ram_4_7: FTCPE port map (rma/ram_4_7,rma/ram_4_7_T,clk,'0','0');
rma/ram_4_7_T <= ((rma/ram_4_7 AND wr_en AND NOT di(7) AND NOT ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (NOT rma/ram_4_7 AND wr_en AND di(7) AND NOT ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
FTCPE_rma/ram_5_0: FTCPE port map (rma/ram_5_0,rma/ram_5_0_T,clk,'0','0');
rma/ram_5_0_T <= ((rma/ram_5_0 AND wr_en AND NOT di(0) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (NOT rma/ram_5_0 AND wr_en AND di(0) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
FTCPE_rma/ram_5_1: FTCPE port map (rma/ram_5_1,rma/ram_5_1_T,clk,'0','0');
rma/ram_5_1_T <= ((rma/ram_5_1 AND wr_en AND NOT di(1) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (NOT rma/ram_5_1 AND wr_en AND di(1) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
FTCPE_rma/ram_5_2: FTCPE port map (rma/ram_5_2,rma/ram_5_2_T,clk,'0','0');
rma/ram_5_2_T <= ((rma/ram_5_2 AND wr_en AND NOT di(2) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (NOT rma/ram_5_2 AND wr_en AND di(2) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
FTCPE_rma/ram_5_3: FTCPE port map (rma/ram_5_3,rma/ram_5_3_T,clk,'0','0');
rma/ram_5_3_T <= ((rma/ram_5_3 AND wr_en AND NOT di(3) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (NOT rma/ram_5_3 AND wr_en AND di(3) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
FTCPE_rma/ram_5_4: FTCPE port map (rma/ram_5_4,rma/ram_5_4_T,clk,'0','0');
rma/ram_5_4_T <= ((rma/ram_5_4 AND wr_en AND NOT di(4) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (NOT rma/ram_5_4 AND wr_en AND di(4) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
FTCPE_rma/ram_5_5: FTCPE port map (rma/ram_5_5,rma/ram_5_5_T,clk,'0','0');
rma/ram_5_5_T <= ((rma/ram_5_5 AND wr_en AND NOT di(5) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (NOT rma/ram_5_5 AND wr_en AND di(5) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
FTCPE_rma/ram_5_6: FTCPE port map (rma/ram_5_6,rma/ram_5_6_T,clk,'0','0');
rma/ram_5_6_T <= ((rma/ram_5_6 AND wr_en AND NOT di(6) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (NOT rma/ram_5_6 AND wr_en AND di(6) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
FTCPE_rma/ram_5_7: FTCPE port map (rma/ram_5_7,rma/ram_5_7_T,clk,'0','0');
rma/ram_5_7_T <= ((rma/ram_5_7 AND wr_en AND NOT di(7) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (NOT rma/ram_5_7 AND wr_en AND di(7) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
FTCPE_rma/ram_6_0: FTCPE port map (rma/ram_6_0,rma/ram_6_0_T,clk,'0','0');
rma/ram_6_0_T <= ((rma/ram_6_0 AND wr_en AND NOT di(0) AND NOT ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (NOT rma/ram_6_0 AND wr_en AND di(0) AND NOT ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
FTCPE_rma/ram_6_1: FTCPE port map (rma/ram_6_1,rma/ram_6_1_T,clk,'0','0');
rma/ram_6_1_T <= ((rma/ram_6_1 AND wr_en AND NOT di(1) AND NOT ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (NOT rma/ram_6_1 AND wr_en AND di(1) AND NOT ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
FTCPE_rma/ram_6_2: FTCPE port map (rma/ram_6_2,rma/ram_6_2_T,clk,'0','0');
rma/ram_6_2_T <= ((rma/ram_6_2 AND wr_en AND NOT di(2) AND NOT ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (NOT rma/ram_6_2 AND wr_en AND di(2) AND NOT ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
FTCPE_rma/ram_6_3: FTCPE port map (rma/ram_6_3,rma/ram_6_3_T,clk,'0','0');
rma/ram_6_3_T <= ((rma/ram_6_3 AND wr_en AND NOT di(3) AND NOT ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (NOT rma/ram_6_3 AND wr_en AND di(3) AND NOT ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
FTCPE_rma/ram_6_4: FTCPE port map (rma/ram_6_4,rma/ram_6_4_T,clk,'0','0');
rma/ram_6_4_T <= ((rma/ram_6_4 AND wr_en AND NOT di(4) AND NOT ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (NOT rma/ram_6_4 AND wr_en AND di(4) AND NOT ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
FTCPE_rma/ram_6_5: FTCPE port map (rma/ram_6_5,rma/ram_6_5_T,clk,'0','0');
rma/ram_6_5_T <= ((rma/ram_6_5 AND wr_en AND NOT di(5) AND NOT ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (NOT rma/ram_6_5 AND wr_en AND di(5) AND NOT ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
FTCPE_rma/ram_6_6: FTCPE port map (rma/ram_6_6,rma/ram_6_6_T,clk,'0','0');
rma/ram_6_6_T <= ((rma/ram_6_6 AND wr_en AND NOT di(6) AND NOT ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (NOT rma/ram_6_6 AND wr_en AND di(6) AND NOT ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
FTCPE_rma/ram_6_7: FTCPE port map (rma/ram_6_7,rma/ram_6_7_T,clk,'0','0');
rma/ram_6_7_T <= ((rma/ram_6_7 AND wr_en AND NOT di(7) AND NOT ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (NOT rma/ram_6_7 AND wr_en AND di(7) AND NOT ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
FTCPE_rma/ram_7_0: FTCPE port map (rma/ram_7_0,rma/ram_7_0_T,clk,'0','0');
rma/ram_7_0_T <= ((rma/ram_7_0 AND wr_en AND NOT di(0) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (NOT rma/ram_7_0 AND wr_en AND di(0) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
FTCPE_rma/ram_7_1: FTCPE port map (rma/ram_7_1,rma/ram_7_1_T,clk,'0','0');
rma/ram_7_1_T <= ((rma/ram_7_1 AND wr_en AND NOT di(1) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (NOT rma/ram_7_1 AND wr_en AND di(1) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
FTCPE_rma/ram_7_2: FTCPE port map (rma/ram_7_2,rma/ram_7_2_T,clk,'0','0');
rma/ram_7_2_T <= ((rma/ram_7_2 AND wr_en AND NOT di(2) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (NOT rma/ram_7_2 AND wr_en AND di(2) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
FTCPE_rma/ram_7_3: FTCPE port map (rma/ram_7_3,rma/ram_7_3_T,clk,'0','0');
rma/ram_7_3_T <= ((rma/ram_7_3 AND wr_en AND NOT di(3) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (NOT rma/ram_7_3 AND wr_en AND di(3) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
FTCPE_rma/ram_7_4: FTCPE port map (rma/ram_7_4,rma/ram_7_4_T,clk,'0','0');
rma/ram_7_4_T <= ((rma/ram_7_4 AND wr_en AND NOT di(4) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (NOT rma/ram_7_4 AND wr_en AND di(4) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
FTCPE_rma/ram_7_5: FTCPE port map (rma/ram_7_5,rma/ram_7_5_T,clk,'0','0');
rma/ram_7_5_T <= ((rma/ram_7_5 AND wr_en AND NOT di(5) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (NOT rma/ram_7_5 AND wr_en AND di(5) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
FTCPE_rma/ram_7_6: FTCPE port map (rma/ram_7_6,rma/ram_7_6_T,clk,'0','0');
rma/ram_7_6_T <= ((rma/ram_7_6 AND wr_en AND NOT di(6) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (NOT rma/ram_7_6 AND wr_en AND di(6) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
FTCPE_rma/ram_7_7: FTCPE port map (rma/ram_7_7,rma/ram_7_7_T,clk,'0','0');
rma/ram_7_7_T <= ((rma/ram_7_7 AND wr_en AND NOT di(7) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (NOT rma/ram_7_7 AND wr_en AND di(7) AND NOT ys(3)/ys(3)_D2 AND
ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
FTCPE_rma/ram_8_0: FTCPE port map (rma/ram_8_0,rma/ram_8_0_T,clk,'0','0');
rma/ram_8_0_T <= ((rma/ram_8_0 AND wr_en AND NOT di(0) AND ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (NOT rma/ram_8_0 AND wr_en AND di(0) AND ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
FTCPE_rma/ram_8_1: FTCPE port map (rma/ram_8_1,rma/ram_8_1_T,clk,'0','0');
rma/ram_8_1_T <= ((rma/ram_8_1 AND wr_en AND NOT di(1) AND ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (NOT rma/ram_8_1 AND wr_en AND di(1) AND ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
FTCPE_rma/ram_8_2: FTCPE port map (rma/ram_8_2,rma/ram_8_2_T,clk,'0','0');
rma/ram_8_2_T <= ((rma/ram_8_2 AND wr_en AND NOT di(2) AND ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (NOT rma/ram_8_2 AND wr_en AND di(2) AND ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
FTCPE_rma/ram_8_3: FTCPE port map (rma/ram_8_3,rma/ram_8_3_T,clk,'0','0');
rma/ram_8_3_T <= ((rma/ram_8_3 AND wr_en AND NOT di(3) AND ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (NOT rma/ram_8_3 AND wr_en AND di(3) AND ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
FTCPE_rma/ram_8_4: FTCPE port map (rma/ram_8_4,rma/ram_8_4_T,clk,'0','0');
rma/ram_8_4_T <= ((rma/ram_8_4 AND wr_en AND NOT di(4) AND ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (NOT rma/ram_8_4 AND wr_en AND di(4) AND ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
FTCPE_rma/ram_8_5: FTCPE port map (rma/ram_8_5,rma/ram_8_5_T,clk,'0','0');
rma/ram_8_5_T <= ((rma/ram_8_5 AND wr_en AND NOT di(5) AND ys(3)/ys(3)_D2 AND
NOT ys(0)/ys(0)_D⌨️ 快捷键说明
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