ascii.htm

这是一个交织器/解交织器的FPGA实现

FTCPE_rma/ram_13_2: FTCPE port map (rma/ram_13_2,rma/ram_13_2_T,clk,'0','0');
rma/ram_13_2_T <= ((rma/ram_13_2 AND wr_en AND NOT di(2) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (NOT rma/ram_13_2 AND wr_en AND di(2) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));

FTCPE_rma/ram_13_3: FTCPE port map (rma/ram_13_3,rma/ram_13_3_T,clk,'0','0');
rma/ram_13_3_T <= ((rma/ram_13_3 AND wr_en AND NOT di(3) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (NOT rma/ram_13_3 AND wr_en AND di(3) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));

FTCPE_rma/ram_13_4: FTCPE port map (rma/ram_13_4,rma/ram_13_4_T,clk,'0','0');
rma/ram_13_4_T <= ((rma/ram_13_4 AND wr_en AND NOT di(4) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (NOT rma/ram_13_4 AND wr_en AND di(4) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));

FTCPE_rma/ram_13_5: FTCPE port map (rma/ram_13_5,rma/ram_13_5_T,clk,'0','0');
rma/ram_13_5_T <= ((rma/ram_13_5 AND wr_en AND NOT di(5) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (NOT rma/ram_13_5 AND wr_en AND di(5) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));

FTCPE_rma/ram_13_6: FTCPE port map (rma/ram_13_6,rma/ram_13_6_T,clk,'0','0');
rma/ram_13_6_T <= ((rma/ram_13_6 AND wr_en AND NOT di(6) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (NOT rma/ram_13_6 AND wr_en AND di(6) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));

FTCPE_rma/ram_13_7: FTCPE port map (rma/ram_13_7,rma/ram_13_7_T,clk,'0','0');
rma/ram_13_7_T <= ((rma/ram_13_7 AND wr_en AND NOT di(7) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (NOT rma/ram_13_7 AND wr_en AND di(7) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));

FTCPE_rma/ram_14_0: FTCPE port map (rma/ram_14_0,rma/ram_14_0_T,clk,'0','0');
rma/ram_14_0_T <= ((rma/ram_14_0 AND wr_en AND NOT di(0) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_14_0 AND wr_en AND di(0) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_14_1: FTCPE port map (rma/ram_14_1,rma/ram_14_1_T,clk,'0','0');
rma/ram_14_1_T <= ((rma/ram_14_1 AND wr_en AND NOT di(1) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_14_1 AND wr_en AND di(1) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_14_2: FTCPE port map (rma/ram_14_2,rma/ram_14_2_T,clk,'0','0');
rma/ram_14_2_T <= ((rma/ram_14_2 AND wr_en AND NOT di(2) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_14_2 AND wr_en AND di(2) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_14_3: FTCPE port map (rma/ram_14_3,rma/ram_14_3_T,clk,'0','0');
rma/ram_14_3_T <= ((rma/ram_14_3 AND wr_en AND NOT di(3) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_14_3 AND wr_en AND di(3) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_14_4: FTCPE port map (rma/ram_14_4,rma/ram_14_4_T,clk,'0','0');
rma/ram_14_4_T <= ((rma/ram_14_4 AND wr_en AND NOT di(4) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_14_4 AND wr_en AND di(4) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_14_5: FTCPE port map (rma/ram_14_5,rma/ram_14_5_T,clk,'0','0');
rma/ram_14_5_T <= ((rma/ram_14_5 AND wr_en AND NOT di(5) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_14_5 AND wr_en AND di(5) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_14_6: FTCPE port map (rma/ram_14_6,rma/ram_14_6_T,clk,'0','0');
rma/ram_14_6_T <= ((rma/ram_14_6 AND wr_en AND NOT di(6) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_14_6 AND wr_en AND di(6) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_14_7: FTCPE port map (rma/ram_14_7,rma/ram_14_7_T,clk,'0','0');
rma/ram_14_7_T <= ((rma/ram_14_7 AND wr_en AND NOT di(7) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_14_7 AND wr_en AND di(7) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_15_0: FTCPE port map (rma/ram_15_0,rma/ram_15_0_T,clk,'0','0');
rma/ram_15_0_T <= ((rma/ram_15_0 AND wr_en AND NOT di(0) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_15_0 AND wr_en AND di(0) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_15_1: FTCPE port map (rma/ram_15_1,rma/ram_15_1_T,clk,'0','0');
rma/ram_15_1_T <= ((rma/ram_15_1 AND wr_en AND NOT di(1) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_15_1 AND wr_en AND di(1) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_15_2: FTCPE port map (rma/ram_15_2,rma/ram_15_2_T,clk,'0','0');
rma/ram_15_2_T <= ((rma/ram_15_2 AND wr_en AND NOT di(2) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_15_2 AND wr_en AND di(2) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_15_3: FTCPE port map (rma/ram_15_3,rma/ram_15_3_T,clk,'0','0');
rma/ram_15_3_T <= ((rma/ram_15_3 AND wr_en AND NOT di(3) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_15_3 AND wr_en AND di(3) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_15_4: FTCPE port map (rma/ram_15_4,rma/ram_15_4_T,clk,'0','0');
rma/ram_15_4_T <= ((rma/ram_15_4 AND wr_en AND NOT di(4) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_15_4 AND wr_en AND di(4) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_15_5: FTCPE port map (rma/ram_15_5,rma/ram_15_5_T,clk,'0','0');
rma/ram_15_5_T <= ((rma/ram_15_5 AND wr_en AND NOT di(5) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_15_5 AND wr_en AND di(5) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_15_6: FTCPE port map (rma/ram_15_6,rma/ram_15_6_T,clk,'0','0');
rma/ram_15_6_T <= ((rma/ram_15_6 AND wr_en AND NOT di(6) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_15_6 AND wr_en AND di(6) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_15_7: FTCPE port map (rma/ram_15_7,rma/ram_15_7_T,clk,'0','0');
rma/ram_15_7_T <= ((rma/ram_15_7 AND wr_en AND NOT di(7) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_15_7 AND wr_en AND di(7) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_1_0: FTCPE port map (rma/ram_1_0,rma/ram_1_0_T,clk,'0','0');
rma/ram_1_0_T <= ((rma/ram_1_0 AND wr_en AND NOT di(0) AND NOT ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (NOT rma/ram_1_0 AND wr_en AND di(0) AND NOT ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));

FTCPE_rma/ram_1_1: FTCPE port map (rma/ram_1_1,rma/ram_1_1_T,clk,'0','0');
rma/ram_1_1_T <= ((rma/ram_1_1 AND wr_en AND NOT di(1) AND NOT ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (NOT rma/ram_1_1 AND wr_en AND di(1) AND NOT ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));

FTCPE_rma/ram_1_2: FTCPE port map (rma/ram_1_2,rma/ram_1_2_T,clk,'0','0');
rma/ram_1_2_T <= ((rma/ram_1_2 AND wr_en AND NOT di(2) AND NOT ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (NOT rma/ram_1_2 AND wr_en AND di(2) AND NOT ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));

FTCPE_rma/ram_1_3: FTCPE port map (rma/ram_1_3,rma/ram_1_3_T,clk,'0','0');
rma/ram_1_3_T <= ((rma/ram_1_3 AND wr_en AND NOT di(3) AND NOT ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (NOT rma/ram_1_3 AND wr_en AND di(3) AND NOT ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));

FTCPE_rma/ram_1_4: FTCPE port map (rma/ram_1_4,rma/ram_1_4_T,clk,'0','0');
rma/ram_1_4_T <= ((rma/ram_1_4 AND wr_en AND NOT di(4) AND NOT ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (NOT rma/ram_1_4 AND wr_en AND di(4) AND NOT ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));

FTCPE_rma/ram_1_5: FTCPE port map (rma/ram_1_5,rma/ram_1_5_T,clk,'0','0');
rma/ram_1_5_T <= ((rma/ram_1_5 AND wr_en AND NOT di(5) AND NOT ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (NOT rma/ram_1_5 AND wr_en AND di(5) AND NOT ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));

FTCPE_rma/ram_1_6: FTCPE port map (rma/ram_1_6,rma/ram_1_6_T,clk,'0','0');
rma/ram_1_6_T <= ((rma/ram_1_6 AND wr_en AND NOT di(6) AND NOT ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (NOT rma/ram_1_6 AND wr_en AND di(6) AND NOT ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));

FTCPE_rma/ram_1_7: FTCPE port map (rma/ram_1_7,rma/ram_1_7_T,clk,'0','0');
rma/ram_1_7_T <= ((rma/ram_1_7 AND wr_en AND NOT di(7) AND NOT ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (NOT rma/ram_1_7 AND wr_en AND di(7) AND NOT ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));

FTCPE_rma/ram_2_0: FTCPE port map (rma/ram_2_0,rma/ram_2_0_T,clk,'0','0');
rma/ram_2_0_T <= ((rma/ram_2_0 AND wr_en AND NOT di(0) AND NOT ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_2_0 AND wr_en AND di(0) AND NOT ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_2_1: FTCPE port map (rma/ram_2_1,rma/ram_2_1_T,clk,'0','0');
rma/ram_2_1_T <= ((rma/ram_2_1 AND wr_en AND NOT di(1) AND NOT ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_2_1 AND wr_en AND di(1) AND NOT ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_2_2: FTCPE port map (rma/ram_2_2,rma/ram_2_2_T,clk,'0','0');
rma/ram_2_2_T <= ((rma/ram_2_2 AND wr_en AND NOT di(2) AND NOT ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_2_2 AND wr_en AND di(2) AND NOT ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_2_3: FTCPE port map (rma/ram_2_3,rma/ram_2_3_T,clk,'0','0');
rma/ram_2_3_T <= ((rma/ram_2_3 AND wr_en AND NOT di(3) AND NOT ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_2_3 AND wr_en AND di(3) AND NOT ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_2_4: FTCPE port map (rma/ram_2_4,rma/ram_2_4_T,clk,'0','0');
rma/ram_2_4_T <= ((rma/ram_2_4 AND wr_en AND NOT di(4) AND NOT ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_2_4 AND wr_en AND di(4) AND NOT ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_2_5: FTCPE port map (rma/ram_2_5,rma/ram_2_5_T,clk,'0','0');
rma/ram_2_5_T <= ((rma/ram_2_5 AND wr_en AND NOT di(5) AND NOT ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_2_5 AND wr_en AND di(5) AND NOT ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_2_6: FTCPE port map (rma/ram_2_6,rma/ram_2_6_T,clk,'0','0');
rma/ram_2_6_T <= ((rma/ram_2_6 AND wr_en AND NOT di(6) AND NOT ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_2_6 AND wr_en AND di(6) AND NOT ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_2_7: FTCPE port map (rma/ram_2_7,rma/ram_2_7_T,clk,'0','0');
rma/ram_2_7_T <= ((rma/ram_2_7 AND wr_en AND NOT di(7) AND NOT ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_2_7 AND wr_en AND di(7) AND NOT ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_3_0: FTCPE port map (rma/ram_3_0,rma/ram_3_0_T,clk,'0','0');
rma/ram_3_0_T <= ((rma/ram_3_0 AND wr_en AND NOT di(0) AND NOT ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_3_0 AND wr_en AND di(0) AND NOT ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_3_1: FTCPE port map (rma/ram_3_1,rma/ram_3_1_T,clk,'0','0');
rma/ram_3_1_T <= ((rma/ram_3_1 AND wr_en AND NOT di(1) AND NOT ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_3_1 AND wr_en AND di(1) AND NOT ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_3_2: FTCPE port map (rma/ram_3_2,rma/ram_3_2_T,clk,'0','0');
rma/ram_3_2_T <= ((rma/ram_3_2 AND wr_en AND NOT di(2) AND NOT ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_3_2 AND wr_en AND di(2) AND NOT ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_3_3: FTCPE port map (rma/ram_3_3,rma/ram_3_3_T,clk,'0','0');
rma/ram_3_3_T <= ((rma/ram_3_3 AND wr_en AND NOT di(3) AND NOT ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_3_3 AND wr_en AND di(3) AND NOT ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));