⭐ 欢迎来到虫虫下载站！ | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站
📤 上传资源

📄 ascii.htm

📁 这是一个交织器/解交织器的FPGA实现
💻 HTM
📖 第 1 页 / 共 5 页
字号:
🔍
12345 
	NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (rma/ram_10_7 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND 
	NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (rma/ram_12_7 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND 
	ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (rma/ram_11_7 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND 
	NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (rma/ram_2_7 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND 
	NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (rma/ram_4_7 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND 
	ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (rma/ram_6_7 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND 
	ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (rma/ram_13_7 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND 
	ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (rma/ram_8_7 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND 
	NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (rma/ram_0_7 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND 
	NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (rma/ram_9_7 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND 
	NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (rma/ram_3_7 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND 
	NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (rma/ram_5_7 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND 
	ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));

** Buried Nodes **

FDCPE_ds0: FDCPE port map (ds(0),qs(2),clk,'0','0');

FDCPE_ds1: FDCPE port map (ds(1),qs(3),clk,'0','0');

FDCPE_ds2: FDCPE port map (ds(2),qs(0),clk,'0','0');

FDCPE_ds3: FDCPE port map (ds(3),qs(1),clk,'0','0');

FTCPE_qs0: FTCPE port map (qs(0),'1',clk,clr,'0',ena);

FTCPE_qs1: FTCPE port map (qs(1),qs(0),clk,clr,'0',ena);

FTCPE_qs2: FTCPE port map (qs(2),qs_T(2),clk,clr,'0',ena);
qs_T(2) <= (qs(0) AND qs(1));

FTCPE_qs3: FTCPE port map (qs(3),qs_T(3),clk,clr,'0',ena);
qs_T(3) <= (qs(0) AND qs(1) AND qs(2));

FDCPE_rd_en: FDCPE port map (rd_en,'0','0','0',NOT sel);

FTCPE_rma/ram_0_0: FTCPE port map (rma/ram_0_0,rma/ram_0_0_T,clk,'0','0');
rma/ram_0_0_T <= ((rma/ram_0_0 AND wr_en AND NOT di(0) AND NOT ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (NOT rma/ram_0_0 AND wr_en AND di(0) AND NOT ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));

FTCPE_rma/ram_0_1: FTCPE port map (rma/ram_0_1,rma/ram_0_1_T,clk,'0','0');
rma/ram_0_1_T <= ((rma/ram_0_1 AND wr_en AND NOT di(1) AND NOT ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (NOT rma/ram_0_1 AND wr_en AND di(1) AND NOT ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));

FTCPE_rma/ram_0_2: FTCPE port map (rma/ram_0_2,rma/ram_0_2_T,clk,'0','0');
rma/ram_0_2_T <= ((rma/ram_0_2 AND wr_en AND NOT di(2) AND NOT ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (NOT rma/ram_0_2 AND wr_en AND di(2) AND NOT ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));

FTCPE_rma/ram_0_3: FTCPE port map (rma/ram_0_3,rma/ram_0_3_T,clk,'0','0');
rma/ram_0_3_T <= ((rma/ram_0_3 AND wr_en AND NOT di(3) AND NOT ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (NOT rma/ram_0_3 AND wr_en AND di(3) AND NOT ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));

FTCPE_rma/ram_0_4: FTCPE port map (rma/ram_0_4,rma/ram_0_4_T,clk,'0','0');
rma/ram_0_4_T <= ((rma/ram_0_4 AND wr_en AND NOT di(4) AND NOT ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (NOT rma/ram_0_4 AND wr_en AND di(4) AND NOT ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));

FTCPE_rma/ram_0_5: FTCPE port map (rma/ram_0_5,rma/ram_0_5_T,clk,'0','0');
rma/ram_0_5_T <= ((rma/ram_0_5 AND wr_en AND NOT di(5) AND NOT ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (NOT rma/ram_0_5 AND wr_en AND di(5) AND NOT ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));

FTCPE_rma/ram_0_6: FTCPE port map (rma/ram_0_6,rma/ram_0_6_T,clk,'0','0');
rma/ram_0_6_T <= ((rma/ram_0_6 AND wr_en AND NOT di(6) AND NOT ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (NOT rma/ram_0_6 AND wr_en AND di(6) AND NOT ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));

FTCPE_rma/ram_0_7: FTCPE port map (rma/ram_0_7,rma/ram_0_7_T,clk,'0','0');
rma/ram_0_7_T <= ((rma/ram_0_7 AND wr_en AND NOT di(7) AND NOT ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (NOT rma/ram_0_7 AND wr_en AND di(7) AND NOT ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));

FTCPE_rma/ram_10_0: FTCPE port map (rma/ram_10_0,rma/ram_10_0_T,clk,'0','0');
rma/ram_10_0_T <= ((rma/ram_10_0 AND wr_en AND NOT di(0) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_10_0 AND wr_en AND di(0) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_10_1: FTCPE port map (rma/ram_10_1,rma/ram_10_1_T,clk,'0','0');
rma/ram_10_1_T <= ((rma/ram_10_1 AND wr_en AND NOT di(1) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_10_1 AND wr_en AND di(1) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_10_2: FTCPE port map (rma/ram_10_2,rma/ram_10_2_T,clk,'0','0');
rma/ram_10_2_T <= ((rma/ram_10_2 AND wr_en AND NOT di(2) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_10_2 AND wr_en AND di(2) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_10_3: FTCPE port map (rma/ram_10_3,rma/ram_10_3_T,clk,'0','0');
rma/ram_10_3_T <= ((rma/ram_10_3 AND wr_en AND NOT di(3) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_10_3 AND wr_en AND di(3) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_10_4: FTCPE port map (rma/ram_10_4,rma/ram_10_4_T,clk,'0','0');
rma/ram_10_4_T <= ((rma/ram_10_4 AND wr_en AND NOT di(4) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_10_4 AND wr_en AND di(4) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_10_5: FTCPE port map (rma/ram_10_5,rma/ram_10_5_T,clk,'0','0');
rma/ram_10_5_T <= ((rma/ram_10_5 AND wr_en AND NOT di(5) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_10_5 AND wr_en AND di(5) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_10_6: FTCPE port map (rma/ram_10_6,rma/ram_10_6_T,clk,'0','0');
rma/ram_10_6_T <= ((rma/ram_10_6 AND wr_en AND NOT di(6) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_10_6 AND wr_en AND di(6) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_10_7: FTCPE port map (rma/ram_10_7,rma/ram_10_7_T,clk,'0','0');
rma/ram_10_7_T <= ((rma/ram_10_7 AND wr_en AND NOT di(7) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_10_7 AND wr_en AND di(7) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_11_0: FTCPE port map (rma/ram_11_0,rma/ram_11_0_T,clk,'0','0');
rma/ram_11_0_T <= ((rma/ram_11_0 AND wr_en AND NOT di(0) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_11_0 AND wr_en AND di(0) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_11_1: FTCPE port map (rma/ram_11_1,rma/ram_11_1_T,clk,'0','0');
rma/ram_11_1_T <= ((rma/ram_11_1 AND wr_en AND NOT di(1) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_11_1 AND wr_en AND di(1) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_11_2: FTCPE port map (rma/ram_11_2,rma/ram_11_2_T,clk,'0','0');
rma/ram_11_2_T <= ((rma/ram_11_2 AND wr_en AND NOT di(2) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_11_2 AND wr_en AND di(2) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_11_3: FTCPE port map (rma/ram_11_3,rma/ram_11_3_T,clk,'0','0');
rma/ram_11_3_T <= ((rma/ram_11_3 AND wr_en AND NOT di(3) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_11_3 AND wr_en AND di(3) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_11_4: FTCPE port map (rma/ram_11_4,rma/ram_11_4_T,clk,'0','0');
rma/ram_11_4_T <= ((rma/ram_11_4 AND wr_en AND NOT di(4) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_11_4 AND wr_en AND di(4) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_11_5: FTCPE port map (rma/ram_11_5,rma/ram_11_5_T,clk,'0','0');
rma/ram_11_5_T <= ((rma/ram_11_5 AND wr_en AND NOT di(5) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_11_5 AND wr_en AND di(5) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_11_6: FTCPE port map (rma/ram_11_6,rma/ram_11_6_T,clk,'0','0');
rma/ram_11_6_T <= ((rma/ram_11_6 AND wr_en AND NOT di(6) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_11_6 AND wr_en AND di(6) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_11_7: FTCPE port map (rma/ram_11_7,rma/ram_11_7_T,clk,'0','0');
rma/ram_11_7_T <= ((rma/ram_11_7 AND wr_en AND NOT di(7) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
	OR (NOT rma/ram_11_7 AND wr_en AND di(7) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));

FTCPE_rma/ram_12_0: FTCPE port map (rma/ram_12_0,rma/ram_12_0_T,clk,'0','0');
rma/ram_12_0_T <= ((rma/ram_12_0 AND wr_en AND NOT di(0) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (NOT rma/ram_12_0 AND wr_en AND di(0) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));

FTCPE_rma/ram_12_1: FTCPE port map (rma/ram_12_1,rma/ram_12_1_T,clk,'0','0');
rma/ram_12_1_T <= ((rma/ram_12_1 AND wr_en AND NOT di(1) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (NOT rma/ram_12_1 AND wr_en AND di(1) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));

FTCPE_rma/ram_12_2: FTCPE port map (rma/ram_12_2,rma/ram_12_2_T,clk,'0','0');
rma/ram_12_2_T <= ((rma/ram_12_2 AND wr_en AND NOT di(2) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (NOT rma/ram_12_2 AND wr_en AND di(2) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));

FTCPE_rma/ram_12_3: FTCPE port map (rma/ram_12_3,rma/ram_12_3_T,clk,'0','0');
rma/ram_12_3_T <= ((rma/ram_12_3 AND wr_en AND NOT di(3) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (NOT rma/ram_12_3 AND wr_en AND di(3) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));

FTCPE_rma/ram_12_4: FTCPE port map (rma/ram_12_4,rma/ram_12_4_T,clk,'0','0');
rma/ram_12_4_T <= ((rma/ram_12_4 AND wr_en AND NOT di(4) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (NOT rma/ram_12_4 AND wr_en AND di(4) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));

FTCPE_rma/ram_12_5: FTCPE port map (rma/ram_12_5,rma/ram_12_5_T,clk,'0','0');
rma/ram_12_5_T <= ((rma/ram_12_5 AND wr_en AND NOT di(5) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (NOT rma/ram_12_5 AND wr_en AND di(5) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));

FTCPE_rma/ram_12_6: FTCPE port map (rma/ram_12_6,rma/ram_12_6_T,clk,'0','0');
rma/ram_12_6_T <= ((rma/ram_12_6 AND wr_en AND NOT di(6) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (NOT rma/ram_12_6 AND wr_en AND di(6) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));

FTCPE_rma/ram_12_7: FTCPE port map (rma/ram_12_7,rma/ram_12_7_T,clk,'0','0');
rma/ram_12_7_T <= ((rma/ram_12_7 AND wr_en AND NOT di(7) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (NOT rma/ram_12_7 AND wr_en AND di(7) AND ys(3)/ys(3)_D2 AND 
	NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));

FTCPE_rma/ram_13_0: FTCPE port map (rma/ram_13_0,rma/ram_13_0_T,clk,'0','0');
rma/ram_13_0_T <= ((rma/ram_13_0 AND wr_en AND NOT di(0) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (NOT rma/ram_13_0 AND wr_en AND di(0) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));

FTCPE_rma/ram_13_1: FTCPE port map (rma/ram_13_1,rma/ram_13_1_T,clk,'0','0');
rma/ram_13_1_T <= ((rma/ram_13_1 AND wr_en AND NOT di(1) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
	OR (NOT rma/ram_13_1 AND wr_en AND di(1) AND ys(3)/ys(3)_D2 AND 
	ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
12345

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -