📄 ascii.htm
字号:
******************************* Equations ********************************
********** UnMapped Logic **********
** Outputs **
FDCPE_do0: FDCPE port map (do(0),do_D(0),clk,'0','0',rd_en);
do_D(0) <= ((rma/ram_15_0 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_7_0 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_14_0 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_1_0 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_10_0 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_12_0 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_11_0 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_2_0 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_4_0 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_6_0 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_13_0 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_8_0 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_0_0 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_9_0 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_3_0 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_5_0 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
FDCPE_do1: FDCPE port map (do(1),do_D(1),clk,'0','0',rd_en);
do_D(1) <= ((rma/ram_15_1 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_7_1 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_14_1 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_1_1 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_10_1 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_12_1 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_11_1 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_2_1 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_4_1 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_6_1 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_13_1 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_8_1 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_0_1 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_9_1 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_3_1 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_5_1 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
FDCPE_do2: FDCPE port map (do(2),do_D(2),clk,'0','0',rd_en);
do_D(2) <= ((rma/ram_15_2 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_7_2 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_14_2 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_1_2 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_10_2 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_12_2 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_11_2 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_2_2 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_4_2 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_6_2 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_13_2 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_8_2 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_0_2 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_9_2 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_3_2 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_5_2 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
FDCPE_do3: FDCPE port map (do(3),do_D(3),clk,'0','0',rd_en);
do_D(3) <= ((rma/ram_15_3 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_7_3 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_14_3 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_1_3 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_10_3 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_12_3 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_11_3 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_2_3 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_4_3 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_6_3 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_13_3 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_8_3 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_0_3 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_9_3 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_3_3 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_5_3 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
FDCPE_do4: FDCPE port map (do(4),do_D(4),clk,'0','0',rd_en);
do_D(4) <= ((rma/ram_15_4 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_7_4 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_14_4 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_1_4 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_10_4 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_12_4 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_11_4 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_2_4 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_4_4 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_6_4 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_13_4 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_8_4 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_0_4 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_9_4 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_3_4 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_5_4 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
FDCPE_do5: FDCPE port map (do(5),do_D(5),clk,'0','0',rd_en);
do_D(5) <= ((rma/ram_15_5 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_7_5 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_14_5 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_1_5 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_10_5 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_12_5 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_11_5 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_2_5 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_4_5 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_6_5 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_13_5 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_8_5 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_0_5 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_9_5 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_3_5 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_5_5 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
FDCPE_do6: FDCPE port map (do(6),do_D(6),clk,'0','0',rd_en);
do_D(6) <= ((rma/ram_15_6 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_7_6 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_14_6 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_1_6 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_10_6 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_12_6 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_11_6 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_2_6 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_4_6 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_6_6 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_13_6 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_8_6 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_0_6 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_9_6 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
OR (rma/ram_3_6 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_5_6 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
FDCPE_do7: FDCPE port map (do(7),do_D(7),clk,'0','0',rd_en);
do_D(7) <= ((rma/ram_15_7 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_7_7 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_14_7 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
OR (rma/ram_1_7 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -