📄 jtop.rpt
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cpldfit: version J.30 Xilinx Inc.
No Fit Report
Design Name: jtop Date: 5- 5-2009, 8:54PM
Device Used: XA95144XL-15-TQ144
Fitting Status: Design Rule Checking Failed
************************** Errors and Warnings ***************************
WARNING:Cpld:828 - Signal 'rd_en.RSTF' has been minimized to 'GND'.
The signal is removed.
WARNING:Cpld:828 - Signal 'wr_en.RSTF' has been minimized to 'GND'.
The signal is removed.
ERROR:Cpld:837 - Insufficient number of macrocells. The design needs at least
151 but only 144 left after allocating other resources.
ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with
the selected implementation options.
************************* Mapped Resource Summary **************************
No logic has been mapped.
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
0 /144 ( 0%) 0 /720 ( 0%) 0 /432 ( 0%) 0 /144 ( 0%) 0 /117 ( 0%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 0/18 0/54 0/90 0/15
FB2 0/18 0/54 0/90 0/15
FB3 0/18 0/54 0/90 0/15
FB4 0/18 0/54 0/90 0/15
FB5 0/18 0/54 0/90 0/14
FB6 0/18 0/54 0/90 0/13
FB7 0/18 0/54 0/90 0/15
FB8 0/18 0/54 0/90 0/15
----- ----- ----- -----
0/144 0/432 0/720 0/117
* - Resource is exhausted
** Global Control Resources **
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 9 0 | I/O : 0 109
Output : 8 0 | GCK/IO : 0 3
Bidirectional : 0 0 | GTS/IO : 0 4
GCK : 1 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 1 0 |
---- ----
Total 19 0
End of Mapped Resource Summary
************************* Summary of UnMapped Logic ************************
** 8 Outputs **
Signal Total Total User
Name Pts Inps Assignment
do<0> 17 21
do<1> 17 21
do<2> 17 21
do<3> 17 21
do<4> 17 21
do<5> 17 21
do<6> 17 21
do<7> 17 21
** 143 Buried Nodes **
Signal Total Total User
Name Pts Inps Assignment
ds<0> 1 1
ds<1> 1 1
ds<2> 1 1
ds<3> 1 1
qs<0> 1 1
qs<1> 2 2
qs<2> 2 3
qs<3> 2 4
rd_en 1 1
rma/ram_0_0 2 7
rma/ram_0_1 2 7
rma/ram_0_2 2 7
rma/ram_0_3 2 7
rma/ram_0_4 2 7
rma/ram_0_5 2 7
rma/ram_0_6 2 7
rma/ram_0_7 2 7
rma/ram_10_0 2 7
rma/ram_10_1 2 7
rma/ram_10_2 2 7
rma/ram_10_3 2 7
rma/ram_10_4 2 7
rma/ram_10_5 2 7
rma/ram_10_6 2 7
rma/ram_10_7 2 7
rma/ram_11_0 2 7
rma/ram_11_1 2 7
rma/ram_11_2 2 7
rma/ram_11_3 2 7
rma/ram_11_4 2 7
rma/ram_11_5 2 7
rma/ram_11_6 2 7
rma/ram_11_7 2 7
rma/ram_12_0 2 7
rma/ram_12_1 2 7
rma/ram_12_2 2 7
rma/ram_12_3 2 7
rma/ram_12_4 2 7
rma/ram_12_5 2 7
rma/ram_12_6 2 7
Signal Total Total User
Name Pts Inps Assignment
rma/ram_12_7 2 7
rma/ram_13_0 2 7
rma/ram_13_1 2 7
rma/ram_13_2 2 7
rma/ram_13_3 2 7
rma/ram_13_4 2 7
rma/ram_13_5 2 7
rma/ram_13_6 2 7
rma/ram_13_7 2 7
rma/ram_14_0 2 7
rma/ram_14_1 2 7
rma/ram_14_2 2 7
rma/ram_14_3 2 7
rma/ram_14_4 2 7
rma/ram_14_5 2 7
rma/ram_14_6 2 7
rma/ram_14_7 2 7
rma/ram_15_0 2 7
rma/ram_15_1 2 7
rma/ram_15_2 2 7
rma/ram_15_3 2 7
rma/ram_15_4 2 7
rma/ram_15_5 2 7
rma/ram_15_6 2 7
rma/ram_15_7 2 7
rma/ram_1_0 2 7
rma/ram_1_1 2 7
rma/ram_1_2 2 7
rma/ram_1_3 2 7
rma/ram_1_4 2 7
rma/ram_1_5 2 7
rma/ram_1_6 2 7
rma/ram_1_7 2 7
rma/ram_2_0 2 7
rma/ram_2_1 2 7
rma/ram_2_2 2 7
rma/ram_2_3 2 7
rma/ram_2_4 2 7
rma/ram_2_5 2 7
rma/ram_2_6 2 7
Signal Total Total User
Name Pts Inps Assignment
rma/ram_2_7 2 7
rma/ram_3_0 2 7
rma/ram_3_1 2 7
rma/ram_3_2 2 7
rma/ram_3_3 2 7
rma/ram_3_4 2 7
rma/ram_3_5 2 7
rma/ram_3_6 2 7
rma/ram_3_7 2 7
rma/ram_4_0 2 7
rma/ram_4_1 2 7
rma/ram_4_2 2 7
rma/ram_4_3 2 7
rma/ram_4_4 2 7
rma/ram_4_5 2 7
rma/ram_4_6 2 7
rma/ram_4_7 2 7
rma/ram_5_0 2 7
rma/ram_5_1 2 7
rma/ram_5_2 2 7
rma/ram_5_3 2 7
rma/ram_5_4 2 7
rma/ram_5_5 2 7
rma/ram_5_6 2 7
rma/ram_5_7 2 7
rma/ram_6_0 2 7
rma/ram_6_1 2 7
rma/ram_6_2 2 7
rma/ram_6_3 2 7
rma/ram_6_4 2 7
rma/ram_6_5 2 7
rma/ram_6_6 2 7
rma/ram_6_7 2 7
rma/ram_7_0 2 7
rma/ram_7_1 2 7
rma/ram_7_2 2 7
rma/ram_7_3 2 7
rma/ram_7_4 2 7
rma/ram_7_5 2 7
rma/ram_7_6 2 7
Signal Total Total User
Name Pts Inps Assignment
rma/ram_7_7 2 7
rma/ram_8_0 2 7
rma/ram_8_1 2 7
rma/ram_8_2 2 7
rma/ram_8_3 2 7
rma/ram_8_4 2 7
rma/ram_8_5 2 7
rma/ram_8_6 2 7
rma/ram_8_7 2 7
rma/ram_9_0 2 7
rma/ram_9_1 2 7
rma/ram_9_2 2 7
rma/ram_9_3 2 7
rma/ram_9_4 2 7
rma/ram_9_5 2 7
rma/ram_9_6 2 7
rma/ram_9_7 2 7
sel 1 4
wr_en 1 1
ys<0>/ys<0>_D2 2 3
ys<1>/ys<1>_D2 2 3
ys<2>/ys<2>_D2 2 3
ys<3>/ys<3>_D2 2 3
** 11 Inputs **
Signal User
Name Assignment
clk
clr
di<0>
di<1>
di<2>
di<3>
di<4>
di<5>
di<6>
di<7>
ena
******************************* Equations ********************************
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