ram_16_8.vhd

来自「这是一个交织器/解交织器的FPGA实现」· VHDL 代码 · 共 49 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ram_16_8 is
port(ad:in std_logic_vector(7 downto 0);		
	  clk:in std_logic;
	  di:in std_logic_vector(7 downto 0);				
	  do:out std_logic_vector(7 downto 0);				
	  wr_en:in std_logic:='0';														
	  rd_en:in std_logic:='0');											
end ram_16_8;

architecture rtl of ram_16_8 is
	subtype ram_word is std_logic_vector(7 downto 0);
	type ram_table is array(0 to 15) of ram_word;
	signal ram:ram_table:=ram_table'(
	ram_word'("00000000"),
	ram_word'("00000000"),
	ram_word'("00000000"),
	ram_word'("00000000"),
	ram_word'("00000000"),
	ram_word'("00000000"),
	ram_word'("00000000"),
	ram_word'("00000000"),
	ram_word'("00000000"),
	ram_word'("00000000"),
	ram_word'("00000000"),
	ram_word'("00000000"),
	ram_word'("00000000"),
	ram_word'("00000000"),
	ram_word'("00000000"),
	ram_word'("00000000"));
	begin
		process(clk)
			begin
				if clk'event and clk='1' then
					if rd_en='1' then
						do<=ram(conv_integer(ad));
					end if;
					if wr_en='1' then
						ram(conv_integer(ad))<=di;
					end if;
				end if;
			end process;
	end rtl;