rom_16_8.vhd

来自「这是一个交织器/解交织器的FPGA实现」· VHDL 代码 · 共 39 行

library ieee;
use ieee.std_logic_1164.all;
entity rom_16_8 is
generic(n:integer:=16);
port(addr:in integer range 0 to n-1;
clk:in std_logic;
data:out std_logic_vector(7 downto 0));
end rom_16_8;
architecture rtl of rom_16_8 is
subtype rom_word is std_logic_vector(7 downto 0);
type rom_table is array(0 to 15)of rom_word;
constant rom:rom_table:=rom_table'(
rom_word'("00000000"),
rom_word'("00000100"),
rom_word'("00001000"),
rom_word'("00001100"),
rom_word'("00000001"),
rom_word'("00000101"),
rom_word'("00001001"),
rom_word'("00001101"),
rom_word'("00000010"),
rom_word'("00000110"),
rom_word'("00001010"),
rom_word'("00001110"),
rom_word'("00000011"),
rom_word'("00000111"),
rom_word'("00001011"),
rom_word'("00001111"));
begin
  process(clk)
  begin
	  if clk'event and clk='1' then
		  data<=rom(addr);
	  end if;
  end process;
end rtl;