mux2.vhd

来自「这是一个交织器/解交织器的FPGA实现」· VHDL 代码 · 共 21 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity mux2 is
generic(n:integer:=16);
	port(d0:in std_logic_vector(7 downto 0);
		  d1:in integer range 0 to n-1;
		  sel:in std_logic;
		  yout:out std_logic_vector(7 downto 0));
end mux2;
architecture if_march of mux2 is 
begin
	process(d0,d1,sel)
	begin
		if(sel='1') then
		yout<=conv_std_logic_vector(d1,8);
		else
		yout<=d0;
		end if;
	end process;
	end if_march;