countern.vhd

来自「这是一个交织器/解交织器的FPGA实现」· VHDL 代码 · 共 35 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity countern is 
generic(n:integer:=16);
port(clr,ena,clk:in std_logic;
	  q:buffer integer range 0 to n-1;			
	  cout:out std_logic);													
end countern;

architecture rtl of countern is 
begin
	process(clk,clr)
begin
	if clr='1' then
		q<=0;
	else
		if clk='1' and clk'event then
			if ena='1' then
				if q=15 then
					q<=0;
				else
					q<=q+1;
				end if;
			end if;
		end if;
	end if;
	if q=15 then
		cout<='1';
	else cout<='0';
	end if;
end process;
end rtl;