📄 jtop.syr
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# Counters : 1 4-bit up counter : 1# Registers : 145 Flip-Flops : 145# Latches : 2 1-bit latch : 2# Multiplexers : 1 8-bit 16-to-1 multiplexer : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================WARNING:Xst:1710 - FF/Latch <data_4> (without init value) has a constant value of 0 in block <rom_16_8>.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <data_5> (without init value) has a constant value of 0 in block <rom_16_8>.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <data_6> (without init value) has a constant value of 0 in block <rom_16_8>.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <data_7> (without init value) has a constant value of 0 in block <rom_16_8>.WARNING:Xst:1426 - The value init of the FF/Latch wr_en hinder the constant cleaning in the block jtop. You should achieve better results by setting this init to 1.WARNING:Xst:1426 - The value init of the FF/Latch rd_en hinder the constant cleaning in the block jtop. You should achieve better results by setting this init to 1.Optimizing unit <jtop> ... implementation constraint: INIT=r : selOptimizing unit <mux2> ...Optimizing unit <rom_16_8> ...Optimizing unit <ram_16_8> ... implementation constraint: INIT=r : ram_4_7 implementation constraint: INIT=r : ram_5_7 implementation constraint: INIT=r : ram_6_7 implementation constraint: INIT=r : ram_7_7 implementation constraint: INIT=r : ram_8_7 implementation constraint: INIT=r : ram_9_7 implementation constraint: INIT=r : ram_10_7 implementation constraint: INIT=r : ram_11_7 implementation constraint: INIT=r : ram_12_7 implementation constraint: INIT=r : ram_13_7 implementation constraint: INIT=r : ram_14_7 implementation constraint: INIT=r : ram_15_7 implementation constraint: INIT=r : ram_0_7 implementation constraint: INIT=r : ram_1_7 implementation constraint: INIT=r : ram_2_7 implementation constraint: INIT=r : ram_3_7 implementation constraint: INIT=r : ram_4_6 implementation constraint: INIT=r : ram_5_6 implementation constraint: INIT=r : ram_6_6 implementation constraint: INIT=r : ram_7_6 implementation constraint: INIT=r : ram_8_6 implementation constraint: INIT=r : ram_9_6 implementation constraint: INIT=r : ram_10_6 implementation constraint: INIT=r : ram_11_6 implementation constraint: INIT=r : ram_12_6 implementation constraint: INIT=r : ram_13_6 implementation constraint: INIT=r : ram_14_6 implementation constraint: INIT=r : ram_15_6 implementation constraint: INIT=r : ram_0_6 implementation constraint: INIT=r : ram_1_6 implementation constraint: INIT=r : ram_2_6 implementation constraint: INIT=r : ram_4_5 implementation constraint: INIT=r : ram_5_5 implementation constraint: INIT=r : ram_6_5 implementation constraint: INIT=r : ram_7_5 implementation constraint: INIT=r : ram_8_5 implementation constraint: INIT=r : ram_9_5 implementation constraint: INIT=r : ram_10_5 implementation constraint: INIT=r : ram_11_5 implementation constraint: INIT=r : ram_12_5 implementation constraint: INIT=r : ram_13_5 implementation constraint: INIT=r : ram_14_5 implementation constraint: INIT=r : ram_15_5 implementation constraint: INIT=r : ram_0_5 implementation constraint: INIT=r : ram_1_5 implementation constraint: INIT=r : ram_2_5 implementation constraint: INIT=r : ram_4_4 implementation constraint: INIT=r : ram_5_4 implementation constraint: INIT=r : ram_6_4 implementation constraint: INIT=r : ram_7_4 implementation constraint: INIT=r : ram_8_4 implementation constraint: INIT=r : ram_9_4 implementation constraint: INIT=r : ram_10_4 implementation constraint: INIT=r : ram_11_4 implementation constraint: INIT=r : ram_12_4 implementation constraint: INIT=r : ram_13_4 implementation constraint: INIT=r : ram_14_4 implementation constraint: INIT=r : ram_15_4 implementation constraint: INIT=r : ram_0_4 implementation constraint: INIT=r : ram_1_4 implementation constraint: INIT=r : ram_2_4 implementation constraint: INIT=r : ram_4_3 implementation constraint: INIT=r : ram_5_3 implementation constraint: INIT=r : ram_6_3 implementation constraint: INIT=r : ram_7_3 implementation constraint: INIT=r : ram_8_3 implementation constraint: INIT=r : ram_9_3 implementation constraint: INIT=r : ram_10_3 implementation constraint: INIT=r : ram_11_3 implementation constraint: INIT=r : ram_12_3 implementation constraint: INIT=r : ram_13_3 implementation constraint: INIT=r : ram_14_3 implementation constraint: INIT=r : ram_15_3 implementation constraint: INIT=r : ram_0_3 implementation constraint: INIT=r : ram_1_3 implementation constraint: INIT=r : ram_2_3 implementation constraint: INIT=r : ram_4_2 implementation constraint: INIT=r : ram_5_2 implementation constraint: INIT=r : ram_6_2 implementation constraint: INIT=r : ram_7_2 implementation constraint: INIT=r : ram_8_2 implementation constraint: INIT=r : ram_9_2 implementation constraint: INIT=r : ram_10_2 implementation constraint: INIT=r : ram_11_2 implementation constraint: INIT=r : ram_12_2 implementation constraint: INIT=r : ram_13_2 implementation constraint: INIT=r : ram_14_2 implementation constraint: INIT=r : ram_15_2 implementation constraint: INIT=r : ram_0_2 implementation constraint: INIT=r : ram_1_2 implementation constraint: INIT=r : ram_2_2 implementation constraint: INIT=r : ram_4_1 implementation constraint: INIT=r : ram_5_1 implementation constraint: INIT=r : ram_6_1 implementation constraint: INIT=r : ram_7_1 implementation constraint: INIT=r : ram_8_1 implementation constraint: INIT=r : ram_9_1 implementation constraint: INIT=r : ram_10_1 implementation constraint: INIT=r : ram_11_1 implementation constraint: INIT=r : ram_12_1 implementation constraint: INIT=r : ram_13_1 implementation constraint: INIT=r : ram_14_1 implementation constraint: INIT=r : ram_15_1 implementation constraint: INIT=r : ram_0_1 implementation constraint: INIT=r : ram_1_1 implementation constraint: INIT=r : ram_2_1 implementation constraint: INIT=r : ram_4_0 implementation constraint: INIT=r : ram_5_0 implementation constraint: INIT=r : ram_6_0 implementation constraint: INIT=r : ram_7_0 implementation constraint: INIT=r : ram_8_0 implementation constraint: INIT=r : ram_9_0 implementation constraint: INIT=r : ram_10_0 implementation constraint: INIT=r : ram_11_0 implementation constraint: INIT=r : ram_12_0 implementation constraint: INIT=r : ram_13_0 implementation constraint: INIT=r : ram_14_0 implementation constraint: INIT=r : ram_15_0 implementation constraint: INIT=r : ram_0_0 implementation constraint: INIT=r : ram_1_0 implementation constraint: INIT=r : ram_2_0 implementation constraint: INIT=r : ram_3_0 implementation constraint: INIT=r : ram_3_1 implementation constraint: INIT=r : ram_3_2 implementation constraint: INIT=r : ram_3_3 implementation constraint: INIT=r : ram_3_4 implementation constraint: INIT=r : ram_3_5 implementation constraint: INIT=r : ram_3_6Optimizing unit <countern> ...=========================================================================* Partition Report *=========================================================================Partition Implementation Status------------------------------- No Partitions were found in this design.-------------------------------=========================================================================* Final Report *=========================================================================Final ResultsRTL Top Level Output File Name : jtop.ngrTop Level Output File Name : jtopOutput Format : NGCOptimization Goal : SpeedKeep Hierarchy : YESTarget Technology : Automotive 9500XLMacro Preserve : YESXOR Preserve : YESClock Enable : YESwysiwyg : NODesign Statistics# IOs : 19Cell Usage :# BELS : 599# AND2 : 300# AND4 : 7# GND : 1# INV : 163# OR2 : 124# VCC : 1# XOR2 : 3# FlipFlops/Latches : 147# FD : 5# FDCE : 140# LD : 2# IO Buffers : 19# IBUF : 11# OBUF : 8=========================================================================CPU : 7.36 / 7.78 s | Elapsed : 8.00 / 8.00 s --> Total memory usage is 128136 kilobytesNumber of errors : 0 ( 0 filtered)Number of warnings : 19 ( 0 filtered)Number of infos : 1 ( 0 filtered)⌨️ 快捷键说明
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