jtop.syr

这是一个交织器/解交织器的FPGA实现

Release 9.1i - xst J.30
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.38 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.38 s | Elapsed : 0.00 / 0.00 s
 
--> Reading design: jtop.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "jtop.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "jtop"
Output Format                      : NGC
Target Device                      : Automotive 9500XL

---- Source Options
Top Module Name                    : jtop
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
Mux Extraction                     : YES
Resource Sharing                   : YES

---- Target Options
Add IO Buffers                     : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Library Search Order               : jtop.lso
Keep Hierarchy                     : YES
RTL Output                         : Yes
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Verilog 2001                       : YES

---- Other Options
Clock Enable                       : YES
wysiwyg                            : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "D:/xjw/4_31/countern.vhd" in Library work.
Entity <countern> compiled.
Entity <countern> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/xjw/4_31/rom_16_8.vhd" in Library work.
Entity <rom_16_8> compiled.
Entity <rom_16_8> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/xjw/4_31/mux2.vhd" in Library work.
Entity <mux2> compiled.
Entity <mux2> (Architecture <if_march>) compiled.
Compiling vhdl file "D:/xjw/4_31/ram_16_8.vhd" in Library work.
Entity <ram_16_8> compiled.
Entity <ram_16_8> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/xjw/4_31/jtop.vhdl" in Library work.
Entity <jtop> compiled.
Entity <jtop> (Architecture <rtl>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <jtop> in library <work> (architecture <rtl>) with generics.
	n = 16

Analyzing hierarchy for entity <countern> in library <work> (architecture <rtl>) with generics.
	n = 16

Analyzing hierarchy for entity <rom_16_8> in library <work> (architecture <rtl>) with generics.
	n = 16

Analyzing hierarchy for entity <mux2> in library <work> (architecture <if_march>) with generics.
	n = 16

Analyzing hierarchy for entity <ram_16_8> in library <work> (architecture <rtl>).


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing generic Entity <jtop> in library <work> (Architecture <rtl>).
	n = 16
INFO:Xst:1739 - HDL ADVISOR - "D:/xjw/4_31/jtop.vhdl" line 7: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
WARNING:Xst:819 - "D:/xjw/4_31/jtop.vhdl" line 81: The following signals are missing in the process sensitivity list:
   sel.
Entity <jtop> analyzed. Unit <jtop> generated.

Analyzing generic Entity <countern> in library <work> (Architecture <rtl>).
	n = 16
WARNING:Xst:819 - "D:/xjw/4_31/countern.vhd" line 13: The following signals are missing in the process sensitivity list:
   q.
Entity <countern> analyzed. Unit <countern> generated.

Analyzing generic Entity <rom_16_8> in library <work> (Architecture <rtl>).
	n = 16
Entity <rom_16_8> analyzed. Unit <rom_16_8> generated.

Analyzing generic Entity <mux2> in library <work> (Architecture <if_march>).
	n = 16
Entity <mux2> analyzed. Unit <mux2> generated.

Analyzing Entity <ram_16_8> in library <work> (Architecture <rtl>).
WARNING:Xst:790 - "D:/xjw/4_31/ram_16_8.vhd" line 38: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "D:/xjw/4_31/ram_16_8.vhd" line 41: Index value(s) does not match array range, simulation mismatch.
Entity <ram_16_8> analyzed. Unit <ram_16_8> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <countern>.
    Related source file is "D:/xjw/4_31/countern.vhd".
    Found 4-bit up counter for signal <q>.
    Summary:
	inferred   1 Counter(s).
Unit <countern> synthesized.


Synthesizing Unit <rom_16_8>.
    Related source file is "D:/xjw/4_31/rom_16_8.vhd".
    Found 16x8-bit ROM for signal <data$mux0000> created at line 33.
    Found 8-bit register for signal <data>.
    Summary:
	inferred   1 ROM(s).
Unit <rom_16_8> synthesized.


Synthesizing Unit <mux2>.
    Related source file is "D:/xjw/4_31/mux2.vhd".
Unit <mux2> synthesized.


Synthesizing Unit <ram_16_8>.
    Related source file is "D:/xjw/4_31/ram_16_8.vhd".
    Found 8-bit register for signal <do>.
    Found 8-bit 16-to-1 multiplexer for signal <do$mux0000> created at line 38.
    Found 128-bit register for signal <ram>.
Unit <ram_16_8> synthesized.


Synthesizing Unit <jtop>.
    Related source file is "D:/xjw/4_31/jtop.vhdl".
WARNING:Xst:737 - Found 1-bit latch for signal <rd_en>.
WARNING:Xst:737 - Found 1-bit latch for signal <wr_en>.
    Found 1-bit register for signal <sel>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <jtop> synthesized.

WARNING:Xst - Property "use_dsp48" is not applicable for this technology.

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 1
 16x8-bit ROM                                          : 1
# Counters                                             : 1
 4-bit up counter                                      : 1
# Registers                                            : 19
 1-bit register                                        : 1
 8-bit register                                        : 18
# Latches                                              : 2
 1-bit latch                                           : 2
# Multiplexers                                         : 1
 8-bit 16-to-1 multiplexer                             : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block rd_en.
   You should achieve better results by setting this init to 1.
WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block wr_en.
   You should achieve better results by setting this init to 1.
WARNING:Xst:1710 - FF/Latch  <7> (without init value) has a constant value of 0 in block <data>.
WARNING:Xst:1710 - FF/Latch  <6> (without init value) has a constant value of 0 in block <data>.
WARNING:Xst:1710 - FF/Latch  <5> (without init value) has a constant value of 0 in block <data>.
WARNING:Xst:1710 - FF/Latch  <4> (without init value) has a constant value of 0 in block <data>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 1
 16x8-bit ROM                                          : 1