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📄 cpldfit.xmsgs

📁 这是一个交织器/解交织器的FPGA实现
💻 XMSGS
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
     by the Xilinx ISE software.  Any direct editing or
     changes made to this file may result in unpredictable
     behavior or data corruption.  It is strongly advised that
     users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="Cpld" num="828" delta="unknown" >Signal &apos;<arg fmt="%s" index="1">rd_en.RSTF</arg>&apos; has been minimized to &apos;<arg fmt="%s" index="2">GND</arg>&apos;.
  The signal is removed.
</msg>

<msg type="warning" file="Cpld" num="828" delta="unknown" >Signal &apos;<arg fmt="%s" index="1">wr_en.RSTF</arg>&apos; has been minimized to &apos;<arg fmt="%s" index="2">GND</arg>&apos;.
  The signal is removed.
</msg>

<msg type="error" file="Cpld" num="837" delta="unknown" >Insufficient number of macrocells. The design needs at least <arg fmt="%d" index="1">151</arg> but only <arg fmt="%d" index="2">144</arg> left after allocating other resources.
</msg>

<msg type="error" file="Cpld" num="868" delta="unknown" >Cannot fit the design into any of the specified devices with the selected implementation options.
</msg>

</messages>

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