block_addgen.vhd

Interleaved Block address generator (customized block size and interleaving strip size).

-- author: yusuf Ibrahim yusuf - Ain shams university - egypt
-- [e-mail]

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;

entity Block_addgen is
	generic(pB: integer:=8;
	        cB: integer:= 32;
			  width: integer:= 72;
			  height :integer:= 32 );
port(
		 reset : in STD_LOGIC;
		 enable : in STD_LOGIC;
		 clk : in STD_LOGIC;
		 finished : out STD_LOGIC;
		 add_out : out STD_LOGIC_VECTOR(15 downto 0)
	     );
end Block_addgen;

architecture Behavioral of Block_addgen is
signal start_reg,start_next : unsigned (15 downto 0):= (others => '0');
signal next_strip_reg,next_strip_next : unsigned (15 downto 0):= (others => '0');
signal r_reg,r_next,start_of_line : unsigned (15 downto 0):= (others => '0');
signal end_of_blk,end_of_strip,end_of_line : std_logic;
begin


process (clk)
begin
if clk' event and clk ='1' then
 if end_of_blk ='1' then
 start_reg <= start_next;
 end if;-- rethink
 if end_of_strip = '1' then
 next_strip_reg <= next_strip_next;
 end if;
 if end_of_line = '1' then
 start_of_line <= r_next;
 end if;
r_reg <= r_next;
end if;
end process;

-- next state logic
start_next <= next_strip_next when end_of_strip ='1' else start_reg + (pB) ;
next_strip_next <= next_strip_reg + (pB*width);
r_next <=(others => '0')    when end_of_blk ='1' else 
         r_reg+(width-cB+1) when end_of_line ='1'  else 
			r_reg +1;

-- flags
end_of_strip <= '1' when start_reg-next_strip_reg >= (width -cB-1) and 
                         end_of_blk = '1' else '0';
end_of_blk <= '1' when r_reg = (cB-1)*(width+1) else '0'; -- rethink
end_of_line <= '1' when r_reg-start_of_line = cB-1 else '0'; 

-- output logic
add_out <= STD_LOGIC_VECTOR(start_reg+r_reg);
finished <= '1' when (start_reg+r_reg) = (height*width) -1 else '0';
end Behavioral;