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从SRAM中读取数据并显示的VHDL源程序

entity top is
    Port (clk:in std_logic;
    		rst:in std_logic;
		rxd:in std_logic;
		ce:out std_logic;
		we:out std_logic;
		oe:out std_logic;
		BHE:out std_logic;
		BLE:out std_logic;
		addr:out std_logic_vector(15 downto 0);
		data:inout std_logic_vector(7 downto 0);
		hs:buffer std_logic;
		vs:buffer std_logic;
		rgb:out std_logic_vector(7 downto 0);
		ledaddr:out std_logic_vector(3 downto 0);
		led:out std_logic_vector(6 downto 0));
end top;

architecture Behavioral of top is

component uartrec is
    Port (clk:in std_logic;
		rxd:in std_logic;
		RxAv:out std_logic;
		data:out std_logic_vector(7 downto 0));
end component;

component wrram is
    Port (clk:in std_logic;
    		rst:in std_logic;
		RxAv:in std_logic;
		din:in std_logic_vector(7 downto 0);
		hloc:in std_logic_vector(9 downto 0);
		vloc:in std_logic_vector(9 downto 0);
		we:out std_logic;
		dout:out std_logic_vector(7 downto 0));
end component;

component wrsram is
    Port (clk:in std_logic;
		RxAv:in std_logic;
		ramwe:in std_logic;
		din:in std_logic_vector(7 downto 0);
		hloc:in std_logic_vector(9 downto 0);
		vloc:in std_logic_vector(9 downto 0);
		SRAM_CE:out std_logic;
		SRAM_WE:out std_logic;
		SRAM_OE:out std_logic;
		BHE:out std_logic;
		BLE:out std_logic;
		we:out std_logic;
		addr:out std_logic_vector(15 downto 0);
		data:inout std_logic_vector(7 downto 0);
		dout:out std_logic_vector(7 downto 0));
end component;

component vgatest is
    port
	(clk : in std_logic;
	 rst: in std_logic;
	 hs: buffer std_logic;
	 vs: buffer std_logic;	
      hloc: out std_logic_vector(9 downto 0);	
      vloc: out std_logic_vector(9 downto 0));
end component;

signal In_data:std_logic_vector(7 downto 0);
signal RxAv:std_logic;
signal weram:std_logic;
signal data_sram:std_logic_vector(7 downto 0);
signal data_ram:std_logic_vector(7 downto 0);
signal wesram:std_logic;
signal vgaclk:std_logic;
signal hloc:std_logic_vector(9 downto 0);
signal vloc:std_logic_vector(9 downto 0);

signal counter:integer range 0 to 50000000;
begin

u0:uartrec port map
    (clk =>clk,
     rxd =>rxd,
	RxAv =>RxAv,
	data =>In_data);

u1:wrram port map
    (clk =>clk,
     rst =>rst,
	RxAv =>RxAv,
	din =>In_data,
	hloc =>hloc,
	vloc =>vloc,
	we =>weram,
	dout =>data_ram);

u2:wrsram port map
    (clk =>clk,
	RxAv =>RxAv,
	ramwe =>weram,
	din =>In_data,
	hloc =>hloc,
	vloc =>vloc,
	SRAM_CE =>ce,
	SRAM_WE =>we,
	SRAM_OE =>oe,
	BHE =>BHE,
	BLE =>BLE,
	we =>wesram,
	addr =>addr,
	data =>data,
	dout =>data_sram);

u4:vgatest port map
    (clk =>clk,
     rst =>rst,
	hs =>hs,
	vs =>vs,
	hloc =>hloc,
	vloc =>vloc);

process(wesram)
begin
  if wesram='1' then
    rgb<=data_ram;
    ledaddr<="0001";
  else
    rgb<=data_ram or data_sram;
    ledaddr<="0010";
  end if;
end process;

process(clk)
begin
  if clk'event and clk='1' then
    counter<=counter+1;
    if counter=50000000 then
      counter<=0;
	 case rgb(2 downto 0) is
	   when "000" =>led<="0000001";  --0
	   when "001" =>led<="1001111";  --1
	   when "010" =>led<="0010010";  --2
	   when "011" =>led<="0000110";  --3
	   when "100" =>led<="1001100";  --4
	   when "101" =>led<="0100100";  --5
	   when "110" =>led<="0100000";  --6
	   when "111" =>led<="0001111";  --7
	   when others =>led<="0110000";
	 end case;
    end if;
  end if;
end process;
end Behavioral;