output.v.bak

来自「用verilog设计的FIR滤波器。滤波器需要很快的处理速度」· BAK 代码 · 共 10 行

module Output(clk,oe,Sum,Yn);
input oe,clk;
output Yn;

always @(posedge clk)
begin
    if(oe==1)
        Yn=Sum;
end
endmodule