input.v

用verilog设计的FIR滤波器。滤波器需要很快的处理速度

module Input(x,reset,clk,num0,num1,num2,num3,num4,num5,num6,num7,num8,num9,num10,num11,num12,num13,num14,num15);
input reset,clk;
input[7:0] x;

output[7:0] num0,num1,num2,num3,num4,num5,num6,num7,num8,num9,num10,num11,num12,num13,num14,num15;
reg[7:0] num0,num1,num2,num3,num4,num5,num6,num7,num8,num9,num10,num11,num12,num13,num14,num15;
always @(posedge reset or posedge clk)
begin
    if(reset)begin
        num0=0;
        num1=0;
        num2=0;
        num3=0;
        num4=0;
        num5=0;
        num6=0;
        num7=0;
        num8=0;
        num9=0;
        num10=0;
        num11=0;
        num12=0;
        num13=0;
        num14=0;
        num15=0;
    end else begin
        num15=num14;
        num14=num13;
        num13=num12;
        num12=num11;
        num11=num10;
        num10=num9;
        num9=num8;
        num8=num7;
        num7=num6;
        num6=num5;
        num5=num4;
        num4=num3;
        num3=num2;
        num2=num1;
        num1=num0;
        num0=x;
    end
end
endmodule