add8.v.bak

来自「用verilog设计的FIR滤波器。滤波器需要很快的处理速度」· BAK 代码 · 共 31 行

module Add8(x,y,ANS);
input[7:0] x,y;
output[8:0] ANS;
reg[8:0] ANS;
wire[3:0] Not0,Not1,Yes1;
wire Nin0,Nin1,Yin1;

AddAhead4 add0(x[3:0],y[3:0],1'b0,Not0,Nin0);
AddAhead4 add1(x[7:4],y[7:4],1'b0,Not1,Nin1);
AddAhead4 add2(x[7:4],y[7:4],1'b1,Yes1,Yin1);

always @(x or y)
begin
    ANS[3:0]=Not0;
    if(Nin0==1)
    begin
        ANS[7:4]=Yes1;
        if(Yin1==1)
            ANS[8]=1'b1;
        else
            ANS[8]=1'b0;
    end else begin
        ANS[7:4]=Not1;
        if(Nin1==1)
            ANS[8]=1'b1;
        else
            ANS[8]=1'b0;
    end
end

endmodule