boothmul.v.bak

用verilog设计的FIR滤波器。滤波器需要很快的处理速度

module BoothMul(A,B,SUM);
input[7:0] A;
input[8:0] B;

output SUM;
wire[15:0] SUM;
reg[9:0] TB,NB,NTB,B0,B1,B2,B3,BB;

WallaceAdd Wadd(B0,B1,B2,B3,SUM);

always @(A or B)
begin
    NB={~{B[8],B[8:0]}+1};
    TB={B[8:0],1'b0};
    NTB=~TB+1;
    BB={B[8],B};
    
    case (A[1:0])
    2'b 00:B0=10'b 0000000000;
    2'b 01:B0=BB;
    2'b 10:B0=NTB;
    2'b 11:B0=NB;
    endcase
    
    case (A[3:1])
    3'b 000:B1=10'b 0000000000;
    3'b 001:B1=BB;
    3'b 010:B1=BB;
    3'b 011:B1=TB;
    3'b 100:B1=NTB;
    3'b 101:B1=NB;
    3'b 110:B1=NB;
    3'b 111:B1=10'b 000000000;
    endcase
    
    case (A[5:3])
    3'b 000:B2=10'b 000000000;
    3'b 001:B2=BB;
    3'b 010:B2=BB;
    3'b 011:B2=TB;
    3'b 100:B2=NTB;
    3'b 101:B2=NB;
    3'b 110:B2=NB;
    3'b 111:B2=10'b 000000000;
    endcase
    
    case (A[7:5])
    3'b 000:B3=10'b 000000000;
    3'b 001:B3=BB;
    3'b 010:B3=BB;
    3'b 011:B3=TB;
    3'b 100:B3=NTB;
    3'b 101:B3=NB;
    3'b 110:B3=NB;
    3'b 111:B3=10'b 000000000;
    endcase
    
end

endmodule