t_booth.v

来自「用verilog设计的FIR滤波器。滤波器需要很快的处理速度」· Verilog 代码 · 共 25 行

module T_Booth();
reg[7:0] A;
reg[8:0] B;
wire [15:0] SUM;
BoothMul boo(A,B,SUM);
initial 
begin
    A=0;
    B=0;
    #10 A=-9;
    #10 B=17;
    #10 A=-121;
    #10 B=234;
    #10 B=-127;
    #10 B=255;
    #10 B=-100;
    #10 A=49;
    #10 B=123;
    #10 B=55;
    #10 A=73;
   #100 $stop;
end

endmodule