firmachine.v.bak

来自「用verilog设计的FIR滤波器。滤波器需要很快的处理速度」· BAK 代码 · 共 25 行

module FirMachine(clk1,clk2,clrn,RESET,X,Y);
input clk1,clk2,clrn,RESET;
input[7:0] X;
output[19:0] Y;

wire[7:0] num0,num1,num2,num3,num4,num5,num6,num7,num8,num9,num10,num11,num12,num13,num14,num15;
wire[7:0] X0,X1,H;
wire[8:0] Xsum;
wire[15:0] X_m_H;
wire[19:0] X_H,Ypart,Ysum,Yfinal;
wire[2:0] sel;

Input    InPut(X,RESET,clk1,num0,num1,num2,num3,num4,num5,num6,num7,num8,num9,num10,num11,num12,num13,num14,num15);
Control  control(clk1,clk2,clrn,reset,oe,sel);
Mux2     mux_X(sel,num0,num1,num2,num3,num4,num5,num6,num7,num8,num9,num10,num11,num12,num13,num14,num15,X0,X1);
Add8     add_8bit(X0,X1,Xsum);
MuxH     mux_H(sel,H);
BoothMul mul(H,Xsum,X_m_H);
assign X_H={{4{X_m_H[15]}},X_m_H};
Add20    add_20bit(X_H,Ysum,Ypart);
SumReg   sumreg(clk2,reset,Ypart,Ysum,Yfinal);
Output   OutPut(clk2,oe,Yfinal,Y);

endmodule