control.v

来自「用verilog设计的FIR滤波器。滤波器需要很快的处理速度」· Verilog 代码 · 共 51 行

module Control (clk1,clk2,clrn,re,oe,sel);
input clk1,clk2,clrn;
output [2:0] sel;
output re,oe;

reg [1:0] state;
reg [2:0] sel;
reg  re,oe,reset;

parameter 	Swait0=2'b00,
           S0=2'b01,
           S1=2'b10,
           Swait1=2'b11;

always @ (posedge clk2 or negedge clrn)
begin
	if(!clrn) begin 
	    state = Swait0;
	    oe=0;
	    sel=0;
	    reset=0;
	end else   	
	case (state)
      	Swait0:
      	    if (!clk1) begin 
      	        oe=0;sel=0;reset=0;
   	       end else begin 
   	           state=S0;oe=0;reset=1;
   	       end
	    S0: if (sel<7)  begin 
	            sel=sel+1;reset=1;oe=0;
	        end else begin  
	            state = S1;reset=1;oe=1;
	        end
	    S1: if (clk1) begin 
	            state=Swait1;oe=0 ; 
	        end else begin 
	            state = Swait0;oe=0;sel=0;reset=0;
	        end
	    Swait1: 
	        if (!clk1) begin  
	            state=Swait0;oe=0;sel=0;reset=0;
	        end
       default:begin  
               state=Swait0;oe=0;sel=0;reset=0;
           end
     endcase   	
     re=!reset;
end
  
endmodule