mux2.v

来自「用verilog设计的FIR滤波器。滤波器需要很快的处理速度」· Verilog 代码 · 共 22 行

module Mux2(sel,num0,num1,num2,num3,num4,num5,num6,num7,num8,num9,num10,num11,num12,num13,num14,num15,X0,X1);

input[2:0] sel;
input[7:0] num0,num1,num2,num3,num4,num5,num6,num7,num8,num9,num10,num11,num12,num13,num14,num15;
output[7:0] X0,X1;
reg[7:0] X0,X1;
always @(sel or num0 or num1 or num2 or num3 or num4 or num5 or num6 or num7 or num8 or num9 or num10 or num11 or num12 or num13 or num14 or num15)
begin
    case (sel)
        3'b000:begin X0=num0;X1=num15;end
        3'b001:begin X0=num1;X1=num14;end
        3'b010:begin X0=num2;X1=num13;end
        3'b011:begin X0=num3;X1=num12;end
        3'b100:begin X0=num4;X1=num11;end
        3'b101:begin X0=num5;X1=num10;end
        3'b110:begin X0=num6;X1=num9;end
        3'b111:begin X0=num7;X1=num8;end
    endcase
end
endmodule