add16.v

用verilog设计的FIR滤波器。滤波器需要很快的处理速度

module Add16(x,y,ANS);
input[15:0] x,y;
output[15:0] ANS;
reg[15:0] ANS;
wire[3:0] Not0,Not1,Not2,Not3,Yes1,Yes2,Yes3;
wire Nin0,Nin1,Nin2,Nin3,Yin1,Yin2,Yin3;

AddAhead4 add0(x[3:0],y[3:0],1'b0,Not0,Nin0);
AddAhead4 add1(x[7:4],y[7:4],1'b0,Not1,Nin1);
AddAhead4 add2(x[7:4],y[7:4],1'b1,Yes1,Yin1);
AddAhead4 add3(x[11:8],y[11:8],1'b0,Not2,Nin2);
AddAhead4 add4(x[11:8],y[11:8],1'b1,Yes2,Yin2);
AddAhead4 add5(x[15:12],y[15:12],1'b0,Not3,Nin3);
AddAhead4 add6(x[15:12],y[15:12],1'b1,Yes3,Yin3);

always @(x or y)
begin
    ANS[3:0]=Not0;
    if(Nin0==1)
    begin
        ANS[7:4]=Yes1;
        if(Yin1==1)
        begin
            ANS[11:8]=Yes2;
            if(Yin2==1)
                ANS[15:12]=Yes3;
            else
                ANS[15:12]=Not3;
        end
        else begin
            ANS[11:8]=Not2;
            if(Nin2==1)
                ANS[15:12]=Yes3;
            else
                ANS[15:12]=Not3;
        end
    end
    else begin
        ANS[7:4]=Not1;
        if(Nin1==1)
        begin
            ANS[11:8]=Yes2;
            if(Yin2==1)
                ANS[15:12]=Yes3;
            else
                ANS[15:12]=Not3;
        end
        else begin
            ANS[11:8]=Not2;
            if(Nin2==1)
                ANS[15:12]=Yes3;
            else
                ANS[15:12]=Not3;
        end
    end
end

endmodule