t_add8.v

用verilog设计的FIR滤波器。滤波器需要很快的处理速度

module T_Add8();
    
reg[7:0] x,y;
wire[8:0] ANS;
Add8 add(x,y,ANS);
initial begin
    x=0;
    y=0;
    #10 x=9;
    #10 y=20;
    #10 x=-19;
    #10 y=127;
    #10 x=127;
    #10 x=-127;
    #10 y=-127;
    #10 $stop;
end
endmodule