arc_clk.v

---简化版

module arc_clk
(
    input clk, // default: 50MHz
    input pci_rst_l,
    output reg clk_1M, clk_200K, clk_100K, clk_25K, clk_12K5, clk_10K, clk_1K
);

    reg [4:0]  cnt_1M;
    reg [6:0]  cnt_200K;
    reg [7:0]  cnt_100K;
    reg [9:0]  cnt_25K;
    reg [10:0] cnt_12K5;
    reg [11:0] cnt_10K;
    reg [14:0] cnt_1K;
    wire load_1M_F, load_200K_F, load_100K_F, load_25K_F, load_12K5_F, load_10K_F, load_1K_F;
    
    assign load_1M_F   = (cnt_1M   == 5'd24)    ? 1'b1 : 1'b0;
    assign load_200K_F = (cnt_200K == 7'd124)   ? 1'b1 : 1'b0; 
    assign load_100K_F = (cnt_100K == 8'd249)   ? 1'b1 : 1'b0; 
    assign load_25K_F  = (cnt_25K  == 10'd999)  ? 1'b1 : 1'b0; 
    assign load_12K5_F = (cnt_12K5 == 11'd1999) ? 1'b1 : 1'b0; 
    assign load_10K_F  = (cnt_10K  == 12'd2499) ? 1'b1 : 1'b0; 
    assign load_1K_F   = (cnt_1K   == 15'd24999)? 1'b1 : 1'b0;
    
    always @ (posedge clk or negedge pci_rst_l) 
	begin
		if (pci_rst_l == 1'b0) 
            cnt_1M <= 0;
        else if (load_1M_F) begin 
            clk_1M <= ~clk_1M;      // the 1MHz clock output;
            cnt_1M <= 0;
            end
        else
            cnt_1M <= cnt_1M + 5'b1;

		if (pci_rst_l == 1'b0) 
            cnt_200K <= 0;
        else if (load_200K_F) begin 
            clk_200K <= ~clk_200K;      // the 200KHz clock output;
            cnt_200K <= 0;
            end
        else
            cnt_200K <= cnt_200K + 7'b1;

		if (pci_rst_l == 1'b0) 
            cnt_100K <= 0;
        else if (load_100K_F) begin 
            clk_100K <= ~clk_100K;      // the 100KHz clock output;
            cnt_100K <= 0;
            end
        else
            cnt_100K <= cnt_100K + 8'b1;

		if (pci_rst_l == 1'b0) 
            cnt_25K <= 0;
        else if (load_25K_F) begin 
            clk_25K <= ~clk_25K;      // the 25KHz clock output;
            cnt_25K <= 0;
            end
        else
            cnt_25K <= cnt_25K + 10'b1;

		if (pci_rst_l == 1'b0) 
            cnt_12K5 <= 0;
        else if (load_12K5_F) begin 
            clk_12K5 <= ~clk_12K5;      // the 12.5KHz clock output;
            cnt_12K5 <= 0;
            end
        else
            cnt_12K5 <= cnt_12K5 + 11'b1;

		if (pci_rst_l == 1'b0) 
            cnt_10K <= 0;
        else if (load_10K_F) begin 
            clk_10K <= ~clk_10K;      // the 10KHz clock output;
            cnt_10K <= 0;
            end
        else
            cnt_10K <= cnt_10K + 12'b1;

		if (pci_rst_l == 1'b0) 
            cnt_1K <= 0;
        else if (load_1K_F) begin 
            clk_1K <= ~clk_1K;      // the 1KHz clock output;
            cnt_1K <= 0;
            end
        else
            cnt_1K <= cnt_1K + 15'b1;
	end 

endmodule