mcst_tx_one.v

---简化版

module mcst_tx_one
(
	input pci_rst_l,    // 计算机系统复位信号
	input [31:0] data,  // 待发送数据
	input clk,          // 计算机系统（pci）总线时钟33MHz
	input tx_clk,       // 发送时钟（20K）
	output reg [3:0] addr,
	output q           // 输出的总线数据
);

	parameter Val_0 = 2'b10;
	parameter Val_1 = 2'b01;
	
	reg [7:0] count;
	reg clock;
	wire [71:0] tx_dataa;
	reg [31:0] rdata;
	
    reg [3:0] state;
    parameter   S0  = 4'h0, 
                S1  = 4'h1, 
                S2  = 4'h2, 
                S3  = 4'h3, 
                S4  = 4'h4, 
                S5  = 4'h5, 
                S6  = 4'h6;

     
    assign q = tx_dataa[count];        // 数据总线输出A
    
    assign tx_dataa[23:0] = 24'b0;      // 12位的空闲数据
    assign tx_dataa[31:24] = 8'haa;     // 4位起始0
    assign tx_dataa[33:32] = addr[0] ? Val_1 : Val_0;
    assign tx_dataa[35:34] = addr[1] ? Val_1 : Val_0;
    assign tx_dataa[37:36] = addr[2] ? Val_1 : Val_0;
    assign tx_dataa[39:38] = addr[3] ? Val_1 : Val_0;
    assign tx_dataa[71:40] = rdata;     // 16位的数据
    
    always @ (negedge pci_rst_l or posedge clk) begin // 同步pci时钟与发送时钟
        if (!pci_rst_l) 
            clock <= 1'b0;
        else
            clock <= tx_clk;
        end
    
    always @ (negedge pci_rst_l or posedge clk)
    begin
        if (!pci_rst_l) begin
            state <= S0;
            count <= 7'b0;
            addr  <= 4'b1;
            end
        else 
            case (state)
            S0: // --------------------------准备读取数据
                state <= S1;
            S1: // --------------------------等待数据从buf中读出
                state <= S2;
            S2: begin // --------------------读出数据
                state <= S3;
                rdata <= data;
                end
            S3: begin // --------------------读出数据，准备发送
                    count <= 7'b0;
                    if (clock)  // ----------发送时钟为高电平
                        state <= S4;
                    else
                        state <= S5;
                end
            S4: // --------------------------开始发送数据
                if (count == 7'd72) // ------发送任务结束
                    state <= S6;
                else if (!clock) begin
                    count <= count + 7'd1;
                    state <= S5;
                    end
                else begin
                    count <= count;
                    state <= S4;
                    end
            S5: // --------------------------开始发送数据
                if (count == 7'd72) // ------发送任务结束
                    state <= S6;
                else if (clock) begin
                    count <= count + 7'd1;
                    state <= S4;
                    end
                else begin
                    count <= count;
                    state <= S5;
                    end
            S6: begin // --------------------当前发送任务结束，开始下一个数据的发送
                state <= S0;
                count <= 7'b0;
                if (addr == 4'd13) 
                    addr <= 4'd1;
                else
                    addr  <= addr + 4'b1;
                end
            default: begin
                state <= S0;
                count <= 7'b0;
                addr  <= 4'b1;
                end
            endcase
    end
    
endmodule