retry_count.v

来自「---简化版」· Verilog 代码 · 共 37 行

//	Module  retry_count
/*
   This modules is the data retry counter.  Ifs the PCI Target responds with 
   a retry it must be done during the first data phase of a transaction.
   The target has up to 16 clock tics to respond with the first data phase
   or it must issue a retry.  This counter is enabled and reset from the
   statemachine block.  Once the target is ready to cycle data to the 
   bkend device it will assert base_region0_l or base_region1_l. 
   The bkend device must respond by asserting ready_l within 10 clock tics
   or else this counter block will assert the retry_l signal.  
*/

module  retry_count (pci_clk, count_rst_l, count_en_l, retry_l);
  output retry_l;
  input pci_clk, count_rst_l, count_en_l;
  
  reg [3:0] count;
 
  assign retry_l = (count >= 4'h9) ? 1'b0 : 1'b1;
  
    
  always @ (posedge pci_clk or negedge count_rst_l)
    begin 
      if (count_rst_l == 1'b0) begin 
        count = 4'h0;
      end
      else if (count_en_l == 1'b0) begin 
        count = count + 4'b0001;
      end
      else begin 
	    count = count;
      end
    end 
 
endmodule //end of retry_count