pci_top.v

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//	Module: pci_top
//
//  This block is the top level Verilog module for the Vantis 32 bit 33Mhz
//  PCI Target Reference Design.  It instantiates the following modules:
//    - base_addr_chk.v
//    - config_mux.v
//    - glue.v
//    - pargen.v
//    - retry_count.v
//    - state_machine.v

module pci_top 
    (
/*******************************/  
/**** PCI Target interface *****/
/*******************************/
	
	// ---  address & data  ---
	inout  [31:0] pci_ad,	// pci's data & address bus;
	inout  [3:0]  pci_cbe, 	// pci bus: command & byte enable;
    inout  pci_par,
	
	// ---  interface control  ---
	input  pci_frame_l,     // pci bus frame signal;
	input  pci_irdy_l,      // pci bus
	input  pci_idsel,       // pci bus 
	inout  pci_trdy_l,      // tragart ready;
	inout  pci_stop_l,
	inout  pci_devsel_l,
	
	// ---  address & data  ---
	input pci_rst_l,        // system reset;
	input pci_clk,			// system clock;
	
	// ---  other  ---
	inout pci_inta_l,
	
/********************************/
/*** Backend interface signals **/
/********************************/
    // ---  address & data  ---
	output [31:0] bk_data,  // pci bus data => to back end;
	output [17:0] bk_addr,  // back end address lines; These can be sized.
	input  [31:0] bk_datai, // back end => pci bus;
	input bk_int_l,

	// ---  control  ---
	output bk_ba0_l,
	output bk_ba1_l,
	output r_w_l,  		// read == 1 & write == 0
	output data_write_l,// used as a clock enable for the pci_clk to the bkend device
	output data_read_l,	// the read strobe for the backend device
	output [20:0] tps
    );
    
    
    
    
/*********************************************/
/*  Internal Wire Declarations               */
/*********************************************/
    wire par_out;               // from: pargen
    wire [31:0] pci_addr_reg;   // from: glue
    wire [3:0]  pci_cbe_reg;    // from: glue
    wire        pci_idsel_reg;  // from: glue
    
	wire [31:4] ba0_reg;	    // from: base_addr_chk; The address space required for ba0
    wire [31:4] ba1_reg;	    // from: base_addr_chk; The address space required for ba1
    wire hit_ba0_l, hit_ba1_l;  // from: base_addr_chk; to: state_machine
    
    wire ba0_en, ba1_en;        // from: config_mux;
    wire [31:0] pci_dat_out;    // from: config_mux;
    wire [1:0] com;             // from: config_mux;
    
	wire pci_par_oe;            // from: state_machine;
    wire pci_ad_oe;             // from: state_machine;
/*********************************************/
/*  End Internal Wire Declarations           */
/*********************************************/
    
    
    
    
//------------------------debug-------------------------------
    assign tps[20] = pci_frame_l;
    assign tps[19] = pci_idsel;
    assign tps[18] = pci_irdy_l;
    assign tps[17] = ((pci_cbe == 4'b0111) && com[1] && !pci_frame_l) ? 1'b1 : 1'b0; // Memory Write
    assign tps[16] = ((pci_cbe == 4'b0110) && com[1] && !pci_frame_l) ? 1'b1 : 1'b0; // Memory read
    assign tps[15] = ((pci_ad[31:4] & 28'hFFFF_F00) == ba0_reg) ? 1'b1 : 1'b0;       // hit0
    assign tps[14] = ((pci_ad[31:4] & 28'hFFFF_FFF) == ba1_reg) ? 1'b1 : 1'b0;       // hit1
    assign tps[13] = pci_par_oe;    // enable : parity output
    assign tps[12] = pci_ad_oe;     // enable : pci data output
    assign tps[11] = bk_int_l;      // enable : interrupt
    assign tps[10] = data_write_l;  // write_en = 0; else write disabled;
    assign tps[9]  = data_read_l;   // read_en  = 0; else read disabled;
    assign tps[8]  = r_w_l;         // read == 1 & write == 0
    //assign tps[11:8] = pci_addr_reg[5:2];
    assign tps[7:4] = pci_addr_reg[5:2];    
//--------------------end of debug----------------------------
    
    
    
    
/************************************************/
/** Start of I/O Ring & Glue Logic section   ***/
/***********************************************/
    assign pci_inta_l   = (!bk_int_l) ? 1'b0 : 1'bZ; 	// asynchronous input is passed through
    assign pci_par		= pci_par_oe  ? par_out : 1'bZ;
    assign pci_ad[31:0]	= pci_ad_oe   ? pci_dat_out[31:0] : 32'bz;
    assign pci_cbe[3:0] = pci_ad_oe   ? 4'b0000 : 4'bz;
    
    assign bk_data[31:0] = pci_ad[31:0];
    assign bk_addr[17:0] = pci_addr_reg[19:2];

/*  ------1------
    input pci_clk,          // system clock;
    input pci_rst_l,        // system reset;
    input [31:0] pci_ad,    // pci's data & address bus;
    input [3:0] pci_cbe,    // pci bus: command & byte enable;
    input pci_idsel,        // config cycle;
    input pci_addr_en,        // state_machine's output: OE for PCI address bus
    output reg [31:0] pci_addr_reg, // Address cycle's address
    output reg [3:0] pci_cbe_reg,   // Command cycle's command
    output reg pci_idsel_reg        // config cycle ID
*//*
glue glue1 ( .pci_clk(pci_clk),
             .pci_rst_l(pci_rst_l),
			 .pci_ad(pci_ad),
			 .pci_cbe(pci_cbe),
			 .pci_idsel(pci_idsel),
			 .pci_addr_en(pci_addr_en),
			 .pci_addr_reg(pci_addr_reg),
			 .pci_cbe_reg(pci_cbe_reg),
			 .pci_idsel_reg(pci_idsel_reg)
			);*/
/************************************************/
/*** End of I/O Ring & Glue Logic section   *****/
/************************************************/








/******************************************************/
/** Start Parity Generation Instantiation section   ***/
/******************************************************/

/*  ------2------
    input pci_clk,          // system clock;
    input [3:0]  pci_cbe,   // pci bus's command & byte enable;
    input [31:0] par_data,  // pci bus's or target's data;
    output par_out          // output: parity result 
*/
pargen pargen1 (.pci_clk(pci_clk),
                .pci_cbe(pci_cbe), 
				.par_data(pci_dat_out), 
				.par_out(par_out) 
                );
/******************************************************/
/** End Parity Generation Instantiation section   *****/
/******************************************************/









/******************************************************/
/** Start base_addr_chk Instantiation section       ***/
/** Decodes ifs the address on the PCI bus is       ***/
/** accessing the backend device                    ***/
/******************************************************/

/*  ------3------
    input pci_clk, 	            // The pci_clk
    input pci_rst_l, 	        // The asynchronous reset active low
    input [31:4] pci_ad, 	    // The raw pci_ad data 
    input [31:4] pci_addr_reg,  // The pci address registered
    input ba0_en, 	            // base address 0 clock enable
    input ba1_en, 	            // base address 1 clock enable

    output hit_ba0_l,           // active low output telling the statemachine the
                                // address is a hit in base address 0
    output hit_ba1_l,           // active low output telling the statemachine the
                                // address is a hit in base address 1
    output reg [31:4] ba0_reg,  // The user defined size bits from the config_mux block
    output reg [31:4] ba1_reg   // The user defined size bits from the config_mux block
*/
base_addr_chk  bachk (.pci_clk(pci_clk), 
					  .pci_rst_l(pci_rst_l),
					  .pci_ad(pci_ad[31:4]), 	 
					  .pci_addr_reg(pci_addr_reg[31:4]),
					  .ba0_en(ba0_en), 
					  .ba1_en(ba1_en), 
					  .hit_ba0_l(hit_ba0_l), 
                      .hit_ba1_l(hit_ba1_l), 
					  .ba0_reg(ba0_reg), 
                      .ba1_reg(ba1_reg)
					 );
/******************************************************/
/** End base_addr_chk Instantiation section       *****/
/******************************************************/













/******************************************************/
/** Start config_mux Instantiation section        *****/
/** This block contains the majority of the PCI   *****/
/** Configuration Registers, and the output       *****/
/** data mux for the pci data bus.                *****/
/** The Engineer should set the appropriate       *****/
/** parameters in the config_mux block.           *****/
/******************************************************/

/*  ------4------
    input pci_clk,              // system clock
    input pci_rst_l,            // async reset
    input pci_irdy_l,           // master device is ready;
    input [3:0]  pci_cbe,       // byte enables in
    input [31:0] pci_data,      // pci data
    input [7:0]  pci_addr_reg,	// from: glue; pci address
    input [3:0]  pci_cbe_reg,   // from: glue; config cycle ID
    input        pci_idsel_reg, // from: glue;
    input [31:4] ba0_reg, 	    // from: base_addr_chk; The address space required for ba0
    input [31:4] ba1_reg, 	    // from: base_addr_chk; The address space required for ba1
    input [31:0] bk_data,     // back end data in
    output reg [31:0] pci_dat_out, // the pci output data bus
    output reg [1:0] com,       // The Mem - I/O enable bits of the command reg
    output reg ba0_en,          // base address 0 clock enable
    output reg ba1_en           // base address 1 clock enable
*/
config_mux con_mux (.pci_clk(pci_clk),
					.pci_rst_l(pci_rst_l), 
					.pci_irdy_l(pci_irdy_l),
					.pci_cbe(pci_cbe), 
					.pci_data(pci_ad),          // the raw pci data 
					.pci_addr_reg(pci_addr_reg[7:0]),
					.pci_cbe_reg(pci_cbe_reg),
					.pci_idsel_reg(pci_idsel_reg),
					.ba0_reg(ba0_reg), 
					.ba1_reg(ba1_reg), 
					.bk_data(bk_datai), 
                    .pci_dat_out(pci_dat_out), 
                    .com(com),
					.ba0_en(ba0_en),
					.ba1_en(ba1_en)
					);
 /******************************************************/
/**   End config_mux Instantiation section        *****/
/******************************************************/












/**************************************************/
/** Start State Machine Instantiation section   ***/
/**************************************************/

/*  ------5------
    input pci_rst_l, pci_clk, pci_frame_l, pci_idsel, pci_irdy_l,
    input [3:0]  pci_cbe,   // The command or byte enables 
    input [31:0] pci_ad, 	// raw pci address data bus
    input hit_ba0_l, 		// The pci address is in base address 0
    input hit_ba1_l, 		// The pci address is in base address 1
    input [1:0] com,
    inout  reg devsel_l, 	// input to 3 state
    inout  reg trdy_l, 	    // input to 3 state
    inout  reg stop_l, 	    // input to 3 state
    output reg pci_ad_oe,   // OE for PCI address bus
    output reg par_oe,      // OE control for pci_par
    output reg bk_ba0_l,    // chip selects to the backend 
    output reg bk_ba1_l,    // chip selects to the backend
    output reg r_w_l, 		// read == 1 & write == 0
    output reg data_wr_l, 	// used as a clock enable for the pci_clk to the bkend device
    output reg data_rd_l 	// the read strobe for the backend device
    output reg [31:0] pci_addr_reg, // first clock's address
    output reg [3:0] pci_cbe_reg,   // first clock's command
    output reg pci_idsel_reg        // config cycle ID
*/
state_machine smcn (.pci_rst_l(pci_rst_l), 
					.pci_clk(pci_clk),
					.pci_frame_l(pci_frame_l), 
					.pci_idsel(pci_idsel), 
					.pci_irdy_l(pci_irdy_l), 
					.pci_cbe(pci_cbe),
					.pci_ad(pci_ad),
                    .hit_ba0_l(hit_ba0_l), 
					.hit_ba1_l(hit_ba1_l), 
					.com(com),
					.devsel_l(pci_devsel_l), 
					.trdy_l(pci_trdy_l), 
                    .stop_l(pci_stop_l), 
					.pci_ad_oe(pci_ad_oe), 
					.par_oe(pci_par_oe), 
					.bk_ba0_l(bk_ba0_l),
                    .bk_ba1_l(bk_ba1_l),
					.r_w_l(r_w_l),
					.data_wr_l(data_write_l), 
					.data_rd_l(data_read_l),
					.tps(tps[3:0]),
                    .pci_addr_reg(pci_addr_reg),
                    .pci_cbe_reg(pci_cbe_reg),
                    .pci_idsel_reg(pci_idsel_reg)
                    );
/**************************************************/
/** End State Machine Instantiation section   *****/
/**************************************************/




endmodule // end of pci_top