pargen.v

来自「---简化版」· Verilog 代码 · 共 59 行

//	Module  pargen
/*
   This file is the parity generator block for the 32 bit PCI Target
   reference design. It generates even parity from the pci_cbe and
   par_data signals.  Notice how the parity logic is pipelined
   to meet the critical 11ns Tco timing for pci_par. 
*/

module pargen 
    (
    input pci_clk,          // system clock;
    input [3:0]  pci_cbe,   // pci bus's command & byte enable;
    input [31:0] par_data,  // pci bus's or target's data;
    output par_out          // output: parity result 
    );
    
 reg cbe_reg;
 reg par3, par2, par1, par0;
 reg par_reg;
 
 assign par_out = par_reg;
 
 always @ (par3 or par2 or par1 or par0 or cbe_reg)
   begin 
     case ({par3, par2, par1, par0, cbe_reg})
       5'b00001: par_reg <=  1;
       5'b00010: par_reg <=  1;
       5'b00100: par_reg <=  1;
       5'b00111: par_reg <=  1;
       5'b01000: par_reg <=  1;
       5'b01011: par_reg <=  1;
       5'b01101: par_reg <=  1;
       5'b01110: par_reg <=  1;
       5'b10000: par_reg <=  1;
       5'b10011: par_reg <=  1;
       5'b10101: par_reg <=  1;
       5'b10110: par_reg <=  1;
       5'b11001: par_reg <=  1;
       5'b11010: par_reg <=  1;
       5'b11100: par_reg <=  1;
       5'b11111: par_reg <=  1;
       default:  par_reg <=  0;
     endcase
   end

 always @ (posedge pci_clk)
   begin 
     par3    <= #13 ^par_data[31:24]; 
     par2    <= #13 ^par_data[23:16];
     par1    <= #13 ^par_data[15:8];
     par0    <= #13 ^par_data[7:0];
     cbe_reg <= #13 ^pci_cbe[3:0];
   end
 
endmodule //end of pargen