base_addr_chk.v

---简化版

//	Module  base_addr_chk
/*    This block is purpose is to implement the write only portion of the base address 
      registers ba0_reg and ba1_reg.   ba0_reg and ba1_reg registers are system programmable, 
      and used to decode the start of the base address regions of the backend device.
      When a write is performed  on ba0_reg or ba1_reg the registers in this
      block latch the data.
      When they are read, the system is determining the amount of address
      space required by the back end device. The ba0_reg and ba1_reg Read-Only
      registers contain the size of the address space, and are set BY THE
      DESIGNER in the config_mux block. The outputs of that block are
      inputs to this block. 
      They are used to determine if the address being requested is a
      hit on the target.  The hit_ba0_l and hit_ba1_l are inputs to
      the state machine to tell it to assert dev_sel_l. 
*/

module base_addr_chk 
    (
    input pci_clk, 	            // The pci_clk
    input pci_rst_l, 	        // The asynchronous reset active low
    input [31:4] pci_ad, 	    // The raw pci_ad data 
    input [31:4] pci_addr_reg,  // The pci address registered
    input ba0_en, 	            // base address 0 clock enable
    input ba1_en, 	            // base address 1 clock enable
    output hit_ba0_l,           // active low output telling the statemachine the
                                // address is a hit in base address 0
    output hit_ba1_l,           // active low output telling the statemachine the
                                // address is a hit in base address 1
    output [31:4] ba0_reg,  // The user defined size bits from the config_mux block
    output [31:4] ba1_reg   // The user defined size bits from the config_mux block
    );
    
// The following block contains the write only ba0_reg and ba1_reg registers
// The system software will map the assigned base address into these
// registers.
    `define ADDR_2G     28'h8000_000
    `define ADDR_1G     28'hC000_000
    `define ADDR_512M   28'hE000_000
    `define ADDR_256M   28'hF000_000
    `define ADDR_128M   28'hF800_000
    `define ADDR_64M    28'hFC00_000
    `define ADDR_32M    28'hFE00_000
    `define ADDR_16M    28'hFF00_000
    `define ADDR_8M     28'hFF80_000
    `define ADDR_4M     28'hFFC0_000
    `define ADDR_2M     28'hFFE0_000
    `define ADDR_1M     28'hFFF0_000
    `define ADDR_512K   28'hFFF8_000
    `define ADDR_256K   28'hFFFC_000
    `define ADDR_128K   28'hFFFE_000
    `define ADDR_64K    28'hFFFF_000
    `define ADDR_32K    28'hFFFF_800 
    `define ADDR_16K    28'hFFFF_C00  
    `define ADDR_8K     28'hFFFF_E00 // default: Memory space 
    `define ADDR_4K     28'hFFFF_F00 
    `define ADDR_2K     28'hFFFF_F80  
    `define ADDR_1K     28'hFFFF_FC0
    `define ADDR_512    28'hFFFF_FE0
    `define ADDR_256    28'hFFFF_FF0  
    `define ADDR_128    28'hFFFF_FF8
    `define ADDR_64     28'hFFFF_FFC
    `define ADDR_32     28'hFFFF_FFE
    `define ADDR_16     28'hFFFF_FFF // default: I/O space

    parameter ba0_size = `ADDR_8K; // Used to decode hit_ba0_l
    parameter ba1_size = `ADDR_16; // Used to decode hit_ba1_l
    
    reg [31:4] ba0_r, ba1_r;
  
// write the base address during a config cycle
    always @ (posedge pci_clk or negedge pci_rst_l)
        begin 
            if (pci_rst_l == 1'b0) begin 
                ba0_r <= 28'h0;
                ba1_r <= 28'h0;
            end
            else if (ba0_en == 1'b1) begin 
                ba0_r <= pci_ad[31:4]; 
            end
            else if (ba1_en == 1'b1) begin
                ba1_r <= pci_ad[31:4];
            end
            else begin 
                ba0_r <= ba0_r;
                ba1_r <= ba1_r;
            end
        end
 
 // The following block is the decode used to determine if the address 
 // in the PCI address reg is a located in Base Address Region 0 or 1
    assign hit_ba0_l = ((pci_addr_reg & ba0_size) == ba0_r) ? 1'b0 : 1'b1;
    assign hit_ba1_l = ((pci_addr_reg & ba1_size) == ba0_r) ? 1'b0 : 1'b1;
  
   assign ba0_reg = ba0_r & ba0_size;
   assign ba1_reg = ba1_r & ba1_size;
   
endmodule  //end of base_addr_chk