state_machine.v

---简化版

  	
            rw_wait_hit: begin // 2'th clock : reading & writing cycle;
                tps[2] <= 1;
				if (!hit_ba0_l) begin // *****base address0 R/W
                    cstate   <= `delay rw_wait;
					devsel_l <= `delay 0;  // --- device is selected;
					bk_ba0_l <= `delay 0;  // --- select the 0's base address space to r/w;
					if (read_flag) begin
                        r_w_l     <= `delay 1; // read
						data_rd_l <= `delay 0;
                        end
					else begin 
						r_w_l <= `delay 0;	// write
						end 
                    end
				else if (!hit_ba1_l) begin // *****base address1 R/W
				    cstate   <= `delay rw_wait;
					devsel_l <= `delay 0;  // --- device is selected;
					bk_ba1_l <= `delay 0;  // --- select the 1's base address space to r/w;
					if (read_flag) begin 
                        r_w_l     <= `delay 1; // read
						data_rd_l <= `delay 0;
                        end
					else begin 
						r_w_l <= `delay 0;
						end 
                    end
				else  // *****No hit
                    //cstate <= `delay retry;
                    cstate <= `delay idle;
                end
			  
            retry: begin
                tps[1] <= 1;
				if (!hit_ba0_l) // *****base address0 R/W
                  begin 
					cstate   <= `delay rw_wait;
					devsel_l <= `delay 0;  // --- device is selected;
					bk_ba0_l <= `delay 0;  // --- select the 0's base address space to r/w;
					if (read_flag) 
					  begin 
						r_w_l     <= `delay 1; // read
						data_rd_l <= `delay 0;
					  end
					else begin 
						r_w_l <= `delay 0;	// write
						end 
				  end
				else if (!hit_ba1_l) // *****base address1 R/W
				  begin  
					cstate   <= `delay rw_wait;
					devsel_l <= `delay 0;  // --- device is selected;
					bk_ba1_l <= `delay 0;  // --- select the 1's base address space to r/w;
					if (read_flag) 
					  begin 
						r_w_l     <= `delay 1; // read
						data_rd_l <= `delay 0;
					  end
					else begin 
						r_w_l <= `delay 0;
						end 
				  end
				else  // *****No hit
                    cstate   <= `delay abort;
                end
            abort: begin
                tps[0] <= 1;
				if (!hit_ba0_l) // *****base address0 R/W
                  begin 
					cstate   <= `delay rw_wait;
					devsel_l <= `delay 0;  // --- device is selected;
					bk_ba0_l <= `delay 0;  // --- select the 0's base address space to r/w;
					if (read_flag) 
					  begin 
						r_w_l     <= `delay 1; // read
						data_rd_l <= `delay 0;
					  end
					else begin 
						r_w_l <= `delay 0;	// write
						end 
				  end
				else if (!hit_ba1_l) // *****base address1 R/W
				  begin  
					cstate   <= `delay rw_wait;
					devsel_l <= `delay 0;  // --- device is selected;
					bk_ba1_l <= `delay 0;  // --- select the 1's base address space to r/w;
					if (read_flag) 
					  begin 
						r_w_l     <= `delay 1; // read
						data_rd_l <= `delay 0;
					  end
					else begin 
						r_w_l <= `delay 0;
						end 
				  end
				else  // *****No hit
                    cstate   <= `delay idle;
                end
                
            rw_wait: begin // 3'th clock : reading & writing cycle;
                tps[1] <= 1;
				if (read_flag) begin	// read 
                    cstate    <= `delay read_wait;
					pci_ad_oe <= `delay 1; // enable
					data_rd_l <= `delay 1; // note
                    end
				else begin 	// write 
				 	cstate <= `delay write_wait;
					trdy_l <= `delay 0;
					if (!pci_frame_l) 
						stop_l <= `delay 0;
					else
						stop_l <= `delay 1;
					data_wr_l  <= `delay 0;
                    end
                end

            read_wait: begin // 4'th clock : read cycle;
				 // waiting for the steady data 
                cstate <= `delay read_last;
                trdy_l <= `delay 0;
                if (!pci_frame_l) 
                    stop_l <= `delay 0; 
                else
                    stop_l <= `delay 1;
					data_rd_l  <= `delay 1;
				end
	
            read_last: begin // 5'th clock : read cycle;
                if (!pci_irdy_l) begin
                    cstate   <= `delay backoff;
                    devsel_l <= `delay 1;
					trdy_l   <= `delay 1;
                    //stop_l   <= `delay 1;
                    if (!pci_frame_l) 
                        stop_l <= #1 0;
                    else
                        stop_l <= #1 1;
						par_oe <= `delay 1;
                    end
                else begin // wait for pci_irdy_l == 0
					cstate   <= `delay read_last;
                    trdy_l   <= `delay 0;
                    if (!pci_frame_l)  
                        stop_l <= `delay 0; 
                    else
                        stop_l <= `delay 1;
                    end
				end // end of the last_read;
	
            write_wait: begin // 4'th clock : writing cycle;
                if (!pci_irdy_l)begin // transfer data
                    cstate    <= `delay backoff;
					devsel_l  <= `delay 1;
					trdy_l    <= `delay 1;
					//stop_l    <= `delay 1;
					if (!pci_frame_l) 
						stop_l <= `delay 0;
					else
						stop_l <= `delay 1;
                    data_wr_l  <= `delay 1;  
                    end
				else begin // wait for pci_irdy_l == 0
				    cstate   <= `delay write_wait;
					trdy_l   <= `delay 0;
					if (!pci_frame_l)  
						stop_l <= `delay 0; 
					else
						stop_l <= `delay 1;
					data_wr_l  <= `delay 0; 
                    end
                end

            backoff: begin // exchange time
                cstate      <= `delay idle;
                devsel_l    <= `delay 1'bZ; 
                trdy_l 		<= `delay 1'bZ; 
                stop_l 		<= `delay 1'bZ;
                pci_ad_oe 	<= `delay 0; 
                par_oe 		<= `delay 0; 
                bk_ba0_l    <= `delay 1;
                bk_ba1_l    <= `delay 1;
                data_rd_l   <= `delay 1;
                data_wr_l   <= `delay 1;
                r_w_l 		<= `delay 0;     // default to write
                read_flag 	<= `delay 0;     // default to write
                con_read_flag 	<= `delay 0; // default to write
                tps[0]      <= `delay 1;
                end

            default: begin
                cstate      <= `delay idle;
                devsel_l    <= `delay 1'bZ; 
                trdy_l 		<= `delay 1'bZ; 
                stop_l 		<= `delay 1'bZ;
                pci_ad_oe 	<= `delay 0; 
                par_oe 		<= `delay 0; 
                bk_ba0_l    <= `delay 1;
                bk_ba1_l    <= `delay 1;
                data_rd_l   <= `delay 1;
                data_wr_l   <= `delay 1;
                r_w_l 		<= `delay 0;     // default to write
                read_flag 	<= `delay 0;     // default to write
                con_read_flag 	<= `delay 0; // default to write
                end
            endcase
        end
   end
 
// 总线地址期：锁存pci_cbe, pci_addr 及 pci_idsel 信号。
    /*always @ (pci_frame_l or cstate)
    begin 
        if ((cstate == idle) && !pci_frame_l) 
            pci_addr_en <= #1 1;
        else 
            pci_addr_en <= #1 0;
    end*/

endmodule   //end of state_machine