glue.v

---简化版

//	Module  glue.v
/*
	This module contains  the miscellaneous glue logic required for
	the PCI Target reference design.
	It contains the PCI address registers,
		CBE registers and the IDSEL register. 
	It latches these during the address phase of any PCI transaction.
*/

module glue 
( 
    input pci_clk,          // system clock;
    input pci_rst_l,        // system reset;
    input [31:0] pci_ad,    // pci's data & address bus;
    input [3:0] pci_cbe,    // pci bus: command & byte enable;
    input pci_idsel,        // config cycle;
    input pci_addr_en,      // state_machine's output: OE for PCI address bus
    
    output reg [31:0] pci_addr_reg, // Address cycle's address
    output reg [3:0] pci_cbe_reg,   // Command cycle's command
    output reg pci_idsel_reg        // config cycle ID
);
   
// 总线地址期：锁存pci_cbe, pci_addr 及 pci_idsel 信号。
    always @ (posedge pci_clk or negedge pci_rst_l)
    begin 
        if (pci_rst_l == 1'b0) begin 
            pci_addr_reg  <= #1 32'b0;      // reset regs
            pci_cbe_reg   <= #1  4'b0;
            pci_idsel_reg <= #1  1'b0;
            end
        else if (pci_addr_en == 1'b1) begin 
            pci_addr_reg  <= #1 pci_ad;     // register address
            pci_cbe_reg   <= #1 pci_cbe;
            pci_idsel_reg <= #1 pci_idsel;
            end
        else begin 
            pci_addr_reg  <= #1 pci_addr_reg;
            pci_cbe_reg   <= #1 pci_cbe_reg;
            pci_idsel_reg <= #1 pci_idsel_reg;
            end  
    end

endmodule //end of glue