arc429_top.qsf

---简化版

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		arc429_top_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name DEVICE EP1C6T144C8
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name TOP_LEVEL_ENTITY arc429_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:15:48  OCTOBER 09, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 8.0
set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
set_location_assignment PIN_37 -to pci_ad[27]
set_location_assignment PIN_38 -to pci_ad[26]
set_location_assignment PIN_39 -to pci_ad[25]
set_location_assignment PIN_40 -to pci_ad[24]
set_location_assignment PIN_47 -to pci_ad[23]
set_location_assignment PIN_48 -to pci_ad[22]
set_location_assignment PIN_49 -to pci_ad[21]
set_location_assignment PIN_50 -to pci_ad[20]
set_location_assignment PIN_51 -to pci_ad[19]
set_location_assignment PIN_52 -to pci_ad[18]
set_location_assignment PIN_53 -to pci_ad[17]
set_location_assignment PIN_56 -to pci_ad[16]
set_location_assignment PIN_72 -to pci_ad[15]
set_location_assignment PIN_73 -to pci_ad[14]
set_location_assignment PIN_74 -to pci_ad[13]
set_location_assignment PIN_75 -to pci_ad[12]
set_location_assignment PIN_76 -to pci_ad[11]
set_location_assignment PIN_77 -to pci_ad[10]
set_location_assignment PIN_78 -to pci_ad[9]
set_location_assignment PIN_79 -to pci_ad[8]
set_location_assignment PIN_83 -to pci_ad[7]
set_location_assignment PIN_84 -to pci_ad[6]
set_location_assignment PIN_85 -to pci_ad[5]
set_location_assignment PIN_96 -to pci_ad[4]
set_location_assignment PIN_97 -to pci_ad[3]
set_location_assignment PIN_98 -to pci_ad[2]
set_location_assignment PIN_99 -to pci_ad[1]
set_location_assignment PIN_100 -to pci_ad[0]
set_location_assignment PIN_33 -to pci_ad[31]
set_location_assignment PIN_34 -to pci_ad[30]
set_location_assignment PIN_35 -to pci_ad[29]
set_location_assignment PIN_36 -to pci_ad[28]
set_location_assignment PIN_41 -to pci_cbe[3]
set_location_assignment PIN_57 -to pci_cbe[2]
set_location_assignment PIN_71 -to pci_cbe[1]
set_location_assignment PIN_82 -to pci_cbe[0]
set_location_assignment PIN_28 -to pci_clk
set_location_assignment PIN_61 -to pci_devsel_l
set_location_assignment PIN_58 -to pci_frame_l
set_location_assignment PIN_42 -to pci_idsel
set_location_assignment PIN_11 -to pci_int_l
set_location_assignment PIN_59 -to pci_irdy_l
set_location_assignment PIN_60 -to pci_trdy_l
set_location_assignment PIN_62 -to pci_stop_l
set_location_assignment PIN_10 -to pci_rst_l
set_location_assignment PIN_70 -to pci_par
set_location_assignment PIN_132 -to arc_rx_a[3]
set_location_assignment PIN_134 -to arc_rx_a[2]
set_location_assignment PIN_140 -to arc_rx_a[1]
set_location_assignment PIN_142 -to arc_rx_a[0]
set_location_assignment PIN_133 -to arc_rx_b[3]
set_location_assignment PIN_139 -to arc_rx_b[2]
set_location_assignment PIN_141 -to arc_rx_b[1]
set_location_assignment PIN_143 -to arc_rx_b[0]
set_location_assignment PIN_1 -to arc_tx_b[3]
set_location_assignment PIN_3 -to arc_tx_b[2]
set_location_assignment PIN_5 -to arc_tx_b[1]
set_location_assignment PIN_7 -to arc_tx_b[0]
set_location_assignment PIN_6 -to arc_tx_a[0]
set_location_assignment PIN_4 -to arc_tx_a[1]
set_location_assignment PIN_2 -to arc_tx_a[2]
set_location_assignment PIN_144 -to arc_tx_a[3]
set_location_assignment PIN_103 -to tp[0]
set_location_assignment PIN_104 -to tp[1]
set_location_assignment PIN_105 -to tp[2]
set_location_assignment PIN_106 -to tp[3]
set_location_assignment PIN_107 -to tp[4]
set_location_assignment PIN_108 -to tp[5]
set_location_assignment PIN_109 -to tp[6]
set_location_assignment PIN_110 -to tp[7]
set_location_assignment PIN_111 -to tp[8]
set_location_assignment PIN_112 -to tp[9]
set_location_assignment PIN_113 -to tp[10]
set_location_assignment PIN_114 -to tp[11]
set_location_assignment PIN_119 -to tp[12]
set_location_assignment PIN_120 -to tp[13]
set_location_assignment PIN_121 -to tp[14]
set_location_assignment PIN_122 -to tp[15]
set_location_assignment PIN_123 -to tp[16]
set_location_assignment PIN_124 -to tp[17]
set_location_assignment PIN_125 -to tp[18]
set_location_assignment PIN_128 -to tp[19]
set_location_assignment PIN_129 -to tp[20]
set_location_assignment PIN_130 -to tp[21]
set_location_assignment PIN_131 -to tp[22]
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS ON
set_global_assignment -name FMAX_REQUIREMENT "33 MHz" -section_id pcisysclk
set_instance_assignment -name CLOCK_SETTINGS pcisysclk -to pci_clk
set_location_assignment PIN_16 -to clk
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name FMAX_REQUIREMENT "20 MHz" -section_id device_clk
set_instance_assignment -name CLOCK_SETTINGS device_clk -to clk
set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE arc429_top.cvwf
set_global_assignment -name ENABLE_CLOCK_LATENCY ON
set_global_assignment -name VERILOG_FILE ../mcst_rx/mcst_rx.v
set_global_assignment -name VERILOG_FILE ../mcst_rx/mcst_rx_ctl.v
set_global_assignment -name VERILOG_FILE ../mcst_rx/mcst_rx_fifo.v
set_global_assignment -name VERILOG_FILE ../mcst_tx/mcst_tx.v
set_global_assignment -name VERILOG_FILE ../mcst_tx/mcst_tx_one.v
set_global_assignment -name VERILOG_FILE ../mcst_tx/mcst_tx_ram.v
set_global_assignment -name VERILOG_FILE ../Clock/arc_clk.v
set_global_assignment -name QIP_FILE ../Clock/pll_clk.qip
set_global_assignment -name VERILOG_FILE ../pci_kernel/state_machine.v
set_global_assignment -name VERILOG_FILE ../pci_kernel/base_addr_chk.v
set_global_assignment -name VERILOG_FILE ../pci_kernel/config_mux.v
set_global_assignment -name VERILOG_FILE ../pci_kernel/pargen.v
set_global_assignment -name VERILOG_FILE ../pci_kernel/pci_top.v
set_global_assignment -name ZIP_VECTOR_WAVEFORM_FILE arc429_top.cvwf
set_global_assignment -name BDF_FILE arc429_top.bdf
set_global_assignment -name SEARCH_PATH "h:\\fpga\\htbk0063\\mcst_rx"
set_global_assignment -name SEARCH_PATH "h:\\fpga\\htbk0063\\mcst_tx"
set_global_assignment -name SEARCH_PATH "h:\\fpga\\htbk0063\\clock"
set_global_assignment -name SEARCH_PATH "h:\\fpga\\htbk0063\\pci_kernel"
set_global_assignment -name SEARCH_PATH "h:\\fpga\\htbk0063\\top"