📄 arc429_top.map.rpt
字号:
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Block Design Naming ; Auto ; Auto ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
+--------------------------------------------------------------+--------------------+--------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------+
; ../mcst_rx/mcst_rx.v ; yes ; User Verilog HDL File ; H:/fpga/HTBK0063/mcst_rx/mcst_rx.v ;
; ../mcst_rx/mcst_rx_ctl.v ; yes ; User Verilog HDL File ; H:/fpga/HTBK0063/mcst_rx/mcst_rx_ctl.v ;
; ../mcst_rx/mcst_rx_fifo.v ; yes ; User Verilog HDL File ; H:/fpga/HTBK0063/mcst_rx/mcst_rx_fifo.v ;
; ../mcst_tx/mcst_tx.v ; yes ; User Verilog HDL File ; H:/fpga/HTBK0063/mcst_tx/mcst_tx.v ;
; ../mcst_tx/mcst_tx_one.v ; yes ; User Verilog HDL File ; H:/fpga/HTBK0063/mcst_tx/mcst_tx_one.v ;
; ../mcst_tx/mcst_tx_ram.v ; yes ; User Verilog HDL File ; H:/fpga/HTBK0063/mcst_tx/mcst_tx_ram.v ;
; ../Clock/arc_clk.v ; yes ; User Verilog HDL File ; H:/fpga/HTBK0063/Clock/arc_clk.v ;
; ../Clock/pll_clk.v ; yes ; User Verilog HDL File ; H:/fpga/HTBK0063/Clock/pll_clk.v ;
; ../pci_kernel/state_machine.v ; yes ; User Verilog HDL File ; H:/fpga/HTBK0063/pci_kernel/state_machine.v ;
; ../pci_kernel/base_addr_chk.v ; yes ; User Verilog HDL File ; H:/fpga/HTBK0063/pci_kernel/base_addr_chk.v ;
; ../pci_kernel/config_mux.v ; yes ; User Verilog HDL File ; H:/fpga/HTBK0063/pci_kernel/config_mux.v ;
; ../pci_kernel/pargen.v ; yes ; User Verilog HDL File ; H:/fpga/HTBK0063/pci_kernel/pargen.v ;
; ../pci_kernel/pci_top.v ; yes ; User Verilog HDL File ; H:/fpga/HTBK0063/pci_kernel/pci_top.v ;
; arc429_top.bdf ; yes ; User Block Diagram/Schematic File ; H:/fpga/HTBK0063/Top/arc429_top.bdf ;
; scfifo.tdf ; yes ; Megafunction ; d:/altera/80/quartus/libraries/megafunctions/scfifo.tdf ;
; a_regfifo.inc ; yes ; Megafunction ; d:/altera/80/quartus/libraries/megafunctions/a_regfifo.inc ;
; a_dpfifo.inc ; yes ; Megafunction ; d:/altera/80/quartus/libraries/megafunctions/a_dpfifo.inc ;
; a_i2fifo.inc ; yes ; Megafunction ; d:/altera/80/quartus/libraries/megafunctions/a_i2fifo.inc ;
; a_fffifo.inc ; yes ; Megafunction ; d:/altera/80/quartus/libraries/megafunctions/a_fffifo.inc ;
; a_f2fifo.inc ; yes ; Megafunction ; d:/altera/80/quartus/libraries/megafunctions/a_f2fifo.inc ;
; aglobal80.inc ; yes ; Megafunction ; d:/altera/80/quartus/libraries/megafunctions/aglobal80.inc ;
; db/scfifo_to21.tdf ; yes ; Auto-Generated Megafunction ; H:/fpga/HTBK0063/Top/db/scfifo_to21.tdf ;
; db/a_dpfifo_gg21.tdf ; yes ; Auto-Generated Megafunction ; H:/fpga/HTBK0063/Top/db/a_dpfifo_gg21.tdf ;
; db/altsyncram_7ra1.tdf ; yes ; Auto-Generated Megafunction ; H:/fpga/HTBK0063/Top/db/altsyncram_7ra1.tdf ;
; db/cntr_rta.tdf ; yes ; Auto-Generated Megafunction ; H:/fpga/HTBK0063/Top/db/cntr_rta.tdf ;
; db/cntr_8u6.tdf ; yes ; Auto-Generated Megafunction ; H:/fpga/HTBK0063/Top/db/cntr_8u6.tdf ;
; db/cntr_sta.tdf ; yes ; Auto-Generated Megafunction ; H:/fpga/HTBK0063/Top/db/cntr_sta.tdf ;
; altpll.tdf ; yes ; Megafunction ; d:/altera/80/quartus/libraries/megafunctions/altpll.tdf ;
; stratix_pll.inc ; yes ; Megafunction ; d:/altera/80/quartus/libraries/megafunctions/stratix_pll.inc ;
; stratixii_pll.inc ; yes ; Megafunction ; d:/altera/80/quartus/libraries/megafunctions/stratixii_pll.inc ;
; cycloneii_pll.inc ; yes ; Megafunction ; d:/altera/80/quartus/libraries/megafunctions/cycloneii_pll.inc ;
; altsyncram.tdf ; yes ; Megafunction ; d:/altera/80/quartus/libraries/megafunctions/altsyncram.tdf ;
; stratix_ram_block.inc ; yes ; Megafunction ; d:/altera/80/quartus/libraries/megafunctions/stratix_ram_block.inc ;
; lpm_mux.inc ; yes ; Megafunction ; d:/altera/80/quartus/libraries/megafunctions/lpm_mux.inc ;
; lpm_decode.inc ; yes ; Megafunction ; d:/altera/80/quartus/libraries/megafunctions/lpm_decode.inc ;
; a_rdenreg.inc ; yes ; Megafunction ; d:/altera/80/quartus/libraries/megafunctions/a_rdenreg.inc ;
; altrom.inc ; yes ; Megafunction ; d:/altera/80/quartus/libraries/megafunctions/altrom.inc ;
; altram.inc ; yes ; Megafunction ; d:/altera/80/quartus/libraries/megafunctions/altram.inc ;
; altdpram.inc ; yes ; Megafunction ; d:/altera/80/quartus/libraries/megafunctions/altdpram.inc ;
; altqpram.inc ; yes ; Megafunction ; d:/altera/80/quartus/libraries/megafunctions/altqpram.inc ;
; db/altsyncram_oik1.tdf ; yes ; Auto-Generated Megafunction ; H:/fpga/HTBK0063/Top/db/altsyncram_oik1.tdf ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------+
+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+---------+
; Resource ; Usage ;
+---------------------------------------------+---------+
; Total logic elements ; 848 ;
; -- Combinational with no register ; 426 ;
; -- Register only ; 219 ;
; -- Combinational with a register ; 203 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 377 ;
; -- 3 input functions ; 96 ;
; -- 2 input functions ; 148 ;
; -- 1 input functions ; 7 ;
; -- 0 input functions ; 1 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 782 ;
; -- arithmetic mode ; 66 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 62 ;
; -- asynchronous clear/load mode ; 175 ;
; ; ;
; Total registers ; 422 ;
; Total logic cells in carry chains ; 76 ;
; I/O pins ; 86 ;
; Total memory bits ; 4608 ;
; Total PLLs ; 1 ;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -