arc429_top.map.rpt

---简化版

Analysis & Synthesis report for arc429_top
Fri Mar 20 17:22:51 2009
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. State Machine - |arc429_top|mcst_tx:inst6|mcst_tx_one:tx_ctrl_ch1|state
  9. State Machine - |arc429_top|mcst_rx:inst|mcst_rx_ctl:receive_data|state
 10. State Machine - |arc429_top|pci_top:inst1|state_machine:smcn|cstate
 11. Registers Removed During Synthesis
 12. General Register Statistics
 13. Inverted Register Statistics
 14. Multiplexer Restructuring Statistics (Restructuring Performed)
 15. Source assignments for mcst_rx:inst|mcst_rx_ctl:receive_data|mcst_rx_fifo:rx_Data_FIFO|scfifo:scfifo_component|scfifo_to21:auto_generated|a_dpfifo_gg21:dpfifo|altsyncram_7ra1:FIFOram
 16. Source assignments for mcst_tx:inst6|mcst_tx_ram:data_buf|altsyncram:altsyncram_component|altsyncram_oik1:auto_generated
 17. Parameter Settings for User Entity Instance: pci_top:inst1|base_addr_chk:bachk
 18. Parameter Settings for User Entity Instance: pci_top:inst1|config_mux:con_mux
 19. Parameter Settings for User Entity Instance: pci_top:inst1|state_machine:smcn
 20. Parameter Settings for User Entity Instance: mcst_rx:inst|mcst_rx_ctl:receive_data
 21. Parameter Settings for User Entity Instance: mcst_rx:inst|mcst_rx_ctl:receive_data|mcst_rx_fifo:rx_Data_FIFO|scfifo:scfifo_component
 22. Parameter Settings for User Entity Instance: pll_clk:inst4|altpll:altpll_component
 23. Parameter Settings for User Entity Instance: mcst_tx:inst6|mcst_tx_ram:data_buf|altsyncram:altsyncram_component
 24. Parameter Settings for User Entity Instance: mcst_tx:inst6|mcst_tx_one:tx_ctrl_ch1
 25. scfifo Parameter Settings by Entity Instance
 26. Analysis & Synthesis Messages
 27. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Fri Mar 20 17:22:51 2009    ;
; Quartus II Version          ; 8.0 Build 215 05/29/2008 SJ Full Version ;
; Revision Name               ; arc429_top                               ;
; Top-level Entity Name       ; arc429_top                               ;
; Family                      ; Cyclone                                  ;
; Total logic elements        ; 848                                      ;
; Total pins                  ; 86                                       ;
; Total virtual pins          ; 0                                        ;
; Total memory bits           ; 4,608                                    ;
; DSP block 9-bit elements    ; N/A until Partition Merge                ;
; Total PLLs                  ; 1                                        ;
; Total DLLs                  ; N/A until Partition Merge                ;
+-----------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                          ;
+--------------------------------------------------------------+--------------------+--------------------+
; Option                                                       ; Setting            ; Default Value      ;
+--------------------------------------------------------------+--------------------+--------------------+
; Device                                                       ; EP1C6T144C8        ;                    ;
; Top-level entity name                                        ; arc429_top         ; arc429_top         ;
; Family name                                                  ; Cyclone            ; Stratix II         ;
; Use smart compilation                                        ; Off                ; Off                ;
; Maximum processors allowed for parallel compilation          ; 1                  ; 1                  ;
; Restructure Multiplexers                                     ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                          ; Off                ; Off                ;
; Preserve fewer node names                                    ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                    ; Off                ; Off                ;
; Verilog Version                                              ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                 ; VHDL93             ; VHDL93             ;
; State Machine Processing                                     ; Auto               ; Auto               ;
; Safe State Machine                                           ; Off                ; Off                ;
; Extract Verilog State Machines                               ; On                 ; On                 ;
; Extract VHDL State Machines                                  ; On                 ; On                 ;
; Ignore Verilog initial constructs                            ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                   ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops               ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                      ; On                 ; On                 ;
; Parallel Synthesis                                           ; Off                ; Off                ;
; NOT Gate Push-Back                                           ; On                 ; On                 ;
; Power-Up Don't Care                                          ; On                 ; On                 ;
; Remove Redundant Logic Cells                                 ; Off                ; Off                ;
; Remove Duplicate Registers                                   ; On                 ; On                 ;
; Ignore CARRY Buffers                                         ; Off                ; Off                ;
; Ignore CASCADE Buffers                                       ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                        ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                    ; Off                ; Off                ;
; Ignore LCELL Buffers                                         ; Off                ; Off                ;
; Ignore SOFT Buffers                                          ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                               ; Off                ; Off                ;
; Optimization Technique                                       ; Balanced           ; Balanced           ;
; Carry Chain Length                                           ; 70                 ; 70                 ;