arc429_top.tan.rpt

---简化版

; Clock Hold: 'pll_clk:inst4|altpll:altpll_component|_clk0'  ; 1.032 ns  ; 50.00 MHz ( period = 20.000 ns ) ; N/A                              ; arc_clk:inst7|clk_100K                                                                                                                                 ; arc_clk:inst7|clk_100K                                                                                                                                 ; pll_clk:inst4|altpll:altpll_component|_clk0 ; pll_clk:inst4|altpll:altpll_component|_clk0 ; 0            ;
; Total number of failed paths                               ;           ;                                  ;                                  ;                                                                                                                                                        ;                                                                                                                                                        ;                                             ;                                             ; 0            ;
+------------------------------------------------------------+-----------+----------------------------------+----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------+---------------------------------------------+--------------+


+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                                ;
+---------------------------------------------------------------------+--------------------+------+---------+-------------+
; Option                                                              ; Setting            ; From ; To      ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+---------+-------------+
; Device Name                                                         ; EP1C6T144C8        ;      ;         ;             ;
; Timing Models                                                       ; Final              ;      ;         ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;         ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;         ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;         ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;         ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;         ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;         ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;         ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;         ;             ;
; Enable Clock Latency                                                ; On                 ;      ;         ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;         ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;         ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;         ;             ;
; Number of paths to report                                           ; 200                ;      ;         ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;         ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;         ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;         ;             ;
; Perform Multicorner Analysis                                        ; Off                ;      ;         ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;         ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;         ;             ;
; Clock Settings                                                      ; device_clk         ;      ; clk     ;             ;
; Clock Settings                                                      ; pcisysclk          ;      ; pci_clk ;             ;
+---------------------------------------------------------------------+--------------------+------+---------+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                             ;
+---------------------------------------------+--------------------+------------+------------------+---------------+--------------+------------+-----------------------+---------------------+--------+--------------+
; Clock Node Name                             ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on   ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+---------------------------------------------+--------------------+------------+------------------+---------------+--------------+------------+-----------------------+---------------------+--------+--------------+
; pll_clk:inst4|altpll:altpll_component|_clk0 ;                    ; PLL output ; 50.0 MHz         ; -1.885 ns     ; -1.885 ns    ; device_clk ; 5                     ; 2                   ; AUTO   ;              ;
; pci_clk                                     ; pcisysclk          ; User Pin   ; 33.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --         ; N/A                   ; N/A                 ; N/A    ;              ;
; clk                                         ; device_clk         ; User Pin   ; 20.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --         ; N/A                   ; N/A                 ; N/A    ;              ;
+---------------------------------------------+--------------------+------------+------------------+---------------+--------------+------------+-----------------------+---------------------+--------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'pll_clk:inst4|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                        ;
+-----------+-----------------------------------------------+---------------------------+---------------------------+---------------------------------------------+---------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack     ; Actual fmax (period)                          ; From                      ; To                        ; From Clock                                  ; To Clock                                    ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------+-----------------------------------------------+---------------------------+---------------------------+---------------------------------------------+---------------------------------------------+-----------------------------+---------------------------+-------------------------+
; 14.498 ns ; 181.75 MHz ( period = 5.502 ns )              ; arc_clk:inst7|cnt_100K[6] ; arc_clk:inst7|cnt_100K[5] ; pll_clk:inst4|altpll:altpll_component|_clk0 ; pll_clk:inst4|altpll:altpll_component|_clk0 ; 20.000 ns                   ; 19.739 ns                 ; 5.241 ns                ;
; 14.499 ns ; 181.79 MHz ( period = 5.501 ns )              ; arc_clk:inst7|cnt_100K[6] ; arc_clk:inst7|cnt_100K[4] ; pll_clk:inst4|altpll:altpll_component|_clk0 ; pll_clk:inst4|altpll:altpll_component|_clk0 ; 20.000 ns                   ; 19.739 ns                 ; 5.240 ns                ;
; 14.629 ns ; 186.19 MHz ( period = 5.371 ns )              ; arc_clk:inst7|cnt_100K[6] ; arc_clk:inst7|cnt_100K[1] ; pll_clk:inst4|altpll:altpll_component|_clk0 ; pll_clk:inst4|altpll:altpll_component|_clk0 ; 20.000 ns                   ; 19.739 ns                 ; 5.110 ns                ;