ps.rpt

ps2 vhdl 实现键盘输入 数码管显示ascii码

  _EQ018 = !count1 & !count2 & !count3 & !CS &  RD &  tmpbitvector8
         #  CS &  SavedPA7
         # !RD &  SavedPA7;
  _EQ019 =  count3 & !CS &  RD &  tmpbitvector8 &  _X001;
  _X001  = EXP(!count1 & !count2);

-- Node name is 'INTR2' = ':23' 
-- Equation name is 'INTR2', type is output 
 INTR2   = DFFE( GND $  VCC, !ZHJS, !_EQ020,  VCC,  VCC);
  _EQ020 =  _X002;
  _X002  = EXP(!CS &  RD);

-- Node name is 'PA0' 
-- Equation name is 'PA0', location is LC020, type is output.
 PA0     = LCELL( _EQ021 $  GND);
  _EQ021 = !count1 & !count2 & !count3 & !CS &  tmpbitvector1
         #  count2 &  count3 & !CS &  tmpbitvector1
         #  count1 &  count3 & !CS &  tmpbitvector1;

-- Node name is 'PA1' 
-- Equation name is 'PA1', location is LC019, type is output.
 PA1     = LCELL( _EQ022 $  GND);
  _EQ022 = !count1 & !count2 & !count3 & !CS &  tmpbitvector2
         #  count2 &  count3 & !CS &  tmpbitvector2
         #  count1 &  count3 & !CS &  tmpbitvector2;

-- Node name is 'PA2' 
-- Equation name is 'PA2', location is LC017, type is output.
 PA2     = LCELL( _EQ023 $  GND);
  _EQ023 = !count1 & !count2 & !count3 & !CS &  tmpbitvector3
         #  count2 &  count3 & !CS &  tmpbitvector3
         #  count1 &  count3 & !CS &  tmpbitvector3;

-- Node name is 'PA3' 
-- Equation name is 'PA3', location is LC041, type is output.
 PA3     = LCELL( _EQ024 $  GND);
  _EQ024 = !count1 & !count2 & !count3 & !CS &  tmpbitvector4
         #  count2 &  count3 & !CS &  tmpbitvector4
         #  count1 &  count3 & !CS &  tmpbitvector4;

-- Node name is 'PA4' 
-- Equation name is 'PA4', location is LC064, type is output.
 PA4     = LCELL( _EQ025 $  GND);
  _EQ025 = !count1 & !count2 & !count3 & !CS &  tmpbitvector5
         #  count2 &  count3 & !CS &  tmpbitvector5
         #  count1 &  count3 & !CS &  tmpbitvector5;

-- Node name is 'PA5' 
-- Equation name is 'PA5', location is LC057, type is output.
 PA5     = LCELL( _EQ026 $  GND);
  _EQ026 = !count1 & !count2 & !count3 & !CS &  tmpbitvector6
         #  count2 &  count3 & !CS &  tmpbitvector6
         #  count1 &  count3 & !CS &  tmpbitvector6;

-- Node name is 'PA6' 
-- Equation name is 'PA6', location is LC048, type is output.
 PA6     = LCELL( _EQ027 $  GND);
  _EQ027 = !count1 & !count2 & !count3 & !CS &  tmpbitvector7
         #  count2 &  count3 & !CS &  tmpbitvector7
         #  count1 &  count3 & !CS &  tmpbitvector7;

-- Node name is 'PA7' 
-- Equation name is 'PA7', location is LC062, type is output.
 PA7     = LCELL( _EQ028 $  GND);
  _EQ028 = !count1 & !count2 & !count3 & !CS &  tmpbitvector8
         #  count2 &  count3 & !CS &  tmpbitvector8
         #  count1 &  count3 & !CS &  tmpbitvector8;

-- Node name is ':35' = 'tmpbitvector1' 
-- Equation name is 'tmpbitvector1', location is LC050, type is buried.
tmpbitvector1 = TFFE( _EQ029, !clk,  VCC,  VCC,  VCC);
  _EQ029 =  count0 & !count1 & !count2 & !count3 & !CS &  k_data & 
             !tmpbitvector1
         #  count0 & !count1 & !count2 & !count3 & !CS & !k_data & 
              tmpbitvector1;

-- Node name is ':34' = 'tmpbitvector2' 
-- Equation name is 'tmpbitvector2', location is LC063, type is buried.
tmpbitvector2 = TFFE( _EQ030, !clk,  VCC,  VCC,  VCC);
  _EQ030 = !count0 &  count1 & !count2 & !count3 & !CS &  k_data & 
             !tmpbitvector2
         # !count0 &  count1 & !count2 & !count3 & !CS & !k_data & 
              tmpbitvector2;

-- Node name is ':33' = 'tmpbitvector3' 
-- Equation name is 'tmpbitvector3', location is LC061, type is buried.
tmpbitvector3 = TFFE( _EQ031, !clk,  VCC,  VCC,  VCC);
  _EQ031 =  count0 &  count1 & !count2 & !count3 & !CS &  k_data & 
             !tmpbitvector3
         #  count0 &  count1 & !count2 & !count3 & !CS & !k_data & 
              tmpbitvector3;

-- Node name is ':32' = 'tmpbitvector4' 
-- Equation name is 'tmpbitvector4', location is LC059, type is buried.
tmpbitvector4 = TFFE( _EQ032, !clk,  VCC,  VCC,  VCC);
  _EQ032 = !count0 & !count1 &  count2 & !count3 & !CS &  k_data & 
             !tmpbitvector4
         # !count0 & !count1 &  count2 & !count3 & !CS & !k_data & 
              tmpbitvector4;

-- Node name is ':31' = 'tmpbitvector5' 
-- Equation name is 'tmpbitvector5', location is LC054, type is buried.
tmpbitvector5 = TFFE( _EQ033, !clk,  VCC,  VCC,  VCC);
  _EQ033 =  count0 & !count1 &  count2 & !count3 & !CS &  k_data & 
             !tmpbitvector5
         #  count0 & !count1 &  count2 & !count3 & !CS & !k_data & 
              tmpbitvector5;

-- Node name is ':30' = 'tmpbitvector6' 
-- Equation name is 'tmpbitvector6', location is LC060, type is buried.
tmpbitvector6 = TFFE( _EQ034, !clk,  VCC,  VCC,  VCC);
  _EQ034 = !count0 &  count1 &  count2 & !count3 & !CS &  k_data & 
             !tmpbitvector6
         # !count0 &  count1 &  count2 & !count3 & !CS & !k_data & 
              tmpbitvector6;

-- Node name is ':29' = 'tmpbitvector7' 
-- Equation name is 'tmpbitvector7', location is LC055, type is buried.
tmpbitvector7 = TFFE( _EQ035, !clk,  VCC,  VCC,  VCC);
  _EQ035 =  count0 &  count1 &  count2 & !count3 & !CS &  k_data & 
             !tmpbitvector7
         #  count0 &  count1 &  count2 & !count3 & !CS & !k_data & 
              tmpbitvector7;

-- Node name is ':28' = 'tmpbitvector8' 
-- Equation name is 'tmpbitvector8', location is LC058, type is buried.
tmpbitvector8 = TFFE( _EQ036, !clk,  VCC,  VCC,  VCC);
  _EQ036 = !count0 & !count1 & !count2 &  count3 & !CS &  k_data & 
             !tmpbitvector8
         # !count0 & !count1 & !count2 &  count3 & !CS & !k_data & 
              tmpbitvector8;

-- Node name is 'ZHJS' = ':21' 
-- Equation name is 'ZHJS', type is output 
 ZHJS    = DFFE( _EQ037 $  VCC, !clk, !CS,  VCC,  VCC);
  _EQ037 = !count0 &  count1 & !count2 &  count3;

-- Node name is '|LPM_ADD_SUB:693|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC038', type is buried 
_LC038   = LCELL( count2 $  _EQ038);
  _EQ038 =  count0 &  count1;

-- Node name is '|LPM_ADD_SUB:693|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC039', type is buried 
_LC039   = LCELL( count3 $  _EQ039);
  _EQ039 =  count0 &  count1 &  count2;

-- Node name is '~905~1' 
-- Equation name is '~905~1', location is LC037, type is output.
 ~PIN002 = LCELL( _EQ040 $  VCC);
  _EQ040 = !CS & !RD;



--     Shareable expanders that are duplicated in multiple LABs:
--    _X001 occurs in LABs C, D




Project Information                        d:\maxplus2\maxplus2\example\ps.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 5,645K