📄 ps.rpt
字号:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\maxplus2\maxplus2\example\ps.rpt
ps
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----- LC20 PA0
| +--- LC19 PA1
| | +- LC17 PA2
| | |
| | | Other LABs fed by signals
| | | that feed LAB 'B'
LC | | | | A B C D | Logic cells that feed LAB 'B':
Pin
12 -> * * * | - * * * | <-- CS
44 -> - - - | - - - - | <-- ~PIN001
LC61 -> - - * | - * - * | <-- tmpbitvector3
LC63 -> - * - | - * - * | <-- tmpbitvector2
LC50 -> * - - | - * * * | <-- tmpbitvector1
LC34 -> * * * | - * * * | <-- count3
LC42 -> * * * | - * * * | <-- count2
LC44 -> * * * | - * * * | <-- count1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\maxplus2\maxplus2\example\ps.rpt
ps
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+--------------------------- LC40 data0
| +------------------------- LC36 data3
| | +----------------------- LC35 data6
| | | +--------------------- LC46 INTR2
| | | | +------------------- LC38 |LPM_ADD_SUB:693|addcore:adder|addcore:adder0|result_node2
| | | | | +----------------- LC39 |LPM_ADD_SUB:693|addcore:adder|addcore:adder0|result_node3
| | | | | | +--------------- LC41 PA3
| | | | | | | +------------- LC48 PA6
| | | | | | | | +----------- LC37 ~PIN002
| | | | | | | | | +--------- LC33 ZHJS
| | | | | | | | | | +------- LC34 count3
| | | | | | | | | | | +----- LC42 count2
| | | | | | | | | | | | +--- LC44 count1
| | | | | | | | | | | | | +- LC43 count0
| | | | | | | | | | | | | |
| | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC40 -> * - - - - - - - - - - - - - | - - * - | <-- data0
LC36 -> - * - - - - - - - - - - - - | - - * - | <-- data3
LC35 -> - - * - - - - - - - - - - - | - - * - | <-- data6
LC38 -> - - - - - - - - - - - * - - | - - * - | <-- |LPM_ADD_SUB:693|addcore:adder|addcore:adder0|result_node2
LC39 -> - - - - - - - - - - * - - - | - - * - | <-- |LPM_ADD_SUB:693|addcore:adder|addcore:adder0|result_node3
LC33 -> * * * * - - - - - - - - - - | - - * * | <-- ZHJS
LC34 -> * * * - - * * * - * * * - * | - * * * | <-- count3
LC42 -> * * * - * * * * - * * * - * | - * * * | <-- count2
LC44 -> * * * - * * * * - * * * * * | - * * * | <-- count1
LC43 -> - - - - * * - - - * * * * * | - - * * | <-- count0
Pin
11 -> - - - - - - - - - * * * * * | - - * * | <-- clk
12 -> * * * * - - * * * * * * * * | - * * * | <-- CS
44 -> - - - - - - - - - - - - - - | - - - - | <-- ~PIN001
9 -> * * * * - - - - * - - - - - | - - * * | <-- RD
LC55 -> - - * - - - - * - - - - - - | - - * * | <-- tmpbitvector7
LC59 -> - * - - - - * - - - - - - - | - - * * | <-- tmpbitvector4
LC50 -> * - - - - - - - - - - - - - | - * * * | <-- tmpbitvector1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\maxplus2\maxplus2\example\ps.rpt
ps
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC56 data1
| +----------------------------- LC53 data2
| | +--------------------------- LC52 data4
| | | +------------------------- LC51 data5
| | | | +----------------------- LC49 data7
| | | | | +--------------------- LC64 PA4
| | | | | | +------------------- LC57 PA5
| | | | | | | +----------------- LC62 PA7
| | | | | | | | +--------------- LC58 tmpbitvector8
| | | | | | | | | +------------- LC55 tmpbitvector7
| | | | | | | | | | +----------- LC60 tmpbitvector6
| | | | | | | | | | | +--------- LC54 tmpbitvector5
| | | | | | | | | | | | +------- LC59 tmpbitvector4
| | | | | | | | | | | | | +----- LC61 tmpbitvector3
| | | | | | | | | | | | | | +--- LC63 tmpbitvector2
| | | | | | | | | | | | | | | +- LC50 tmpbitvector1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC56 -> * - - - - - - - - - - - - - - - | - - - * | <-- data1
LC53 -> - * - - - - - - - - - - - - - - | - - - * | <-- data2
LC52 -> - - * - - - - - - - - - - - - - | - - - * | <-- data4
LC51 -> - - - * - - - - - - - - - - - - | - - - * | <-- data5
LC49 -> - - - - * - - - - - - - - - - - | - - - * | <-- data7
LC58 -> - - - - * - - * * - - - - - - - | - - - * | <-- tmpbitvector8
LC55 -> - - - - - - - - - * - - - - - - | - - * * | <-- tmpbitvector7
LC60 -> - - - * - - * - - - * - - - - - | - - - * | <-- tmpbitvector6
LC54 -> - - * - - * - - - - - * - - - - | - - - * | <-- tmpbitvector5
LC59 -> - - - - - - - - - - - - * - - - | - - * * | <-- tmpbitvector4
LC61 -> - * - - - - - - - - - - - * - - | - * - * | <-- tmpbitvector3
LC63 -> * - - - - - - - - - - - - - * - | - * - * | <-- tmpbitvector2
LC50 -> - - - - - - - - - - - - - - - * | - * * * | <-- tmpbitvector1
Pin
11 -> - - - - - - - - * * * * * * * * | - - * * | <-- clk
12 -> * * * * * * * * * * * * * * * * | - * * * | <-- CS
8 -> - - - - - - - - * * * * * * * * | - - - * | <-- k_data
44 -> - - - - - - - - - - - - - - - - | - - - - | <-- ~PIN001
9 -> * * * * * - - - - - - - - - - - | - - * * | <-- RD
LC33 -> * * * * * - - - - - - - - - - - | - - * * | <-- ZHJS
LC34 -> * * * * * * * * * * * * * * * * | - * * * | <-- count3
LC42 -> * * * * * * * * * * * * * * * * | - * * * | <-- count2
LC44 -> * * * * * * * * * * * * * * * * | - * * * | <-- count1
LC43 -> - - - - - - - - * * * * * * * * | - - * * | <-- count0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\maxplus2\maxplus2\example\ps.rpt
ps
** EQUATIONS **
clk : INPUT;
CS : INPUT;
k_data : INPUT;
RD : INPUT;
~PIN001 : INPUT;
-- Node name is ':51' = 'count0'
-- Equation name is 'count0', location is LC043, type is buried.
count0 = TFFE(!_EQ001, !clk, !CS, VCC, VCC);
_EQ001 = count0 & count1 & !count2 & count3;
-- Node name is ':50' = 'count1'
-- Equation name is 'count1', location is LC044, type is buried.
count1 = TFFE( count0, !clk, !CS, VCC, VCC);
-- Node name is ':49' = 'count2'
-- Equation name is 'count2', location is LC042, type is buried.
count2 = DFFE( _EQ002 $ _LC038, !clk, !CS, VCC, VCC);
_EQ002 = count0 & count1 & !count2 & count3 & _LC038;
-- Node name is ':48' = 'count3'
-- Equation name is 'count3', location is LC034, type is buried.
count3 = DFFE( _EQ003 $ _LC039, !clk, !CS, VCC, VCC);
_EQ003 = count0 & count1 & !count2 & count3 & _LC039;
-- Node name is 'data0' = 'SavedPA0'
-- Equation name is 'data0', location is LC040, type is output.
data0 = TRI(SavedPA0, GLOBAL(!~PIN001));
SavedPA0 = DFFE( _EQ004 $ _EQ005, !ZHJS, VCC, VCC, VCC);
_EQ004 = !count1 & !count2 & !count3 & !CS & RD & tmpbitvector1
# CS & SavedPA0
# !RD & SavedPA0;
_EQ005 = count3 & !CS & RD & tmpbitvector1 & _X001;
_X001 = EXP(!count1 & !count2);
-- Node name is 'data1' = 'SavedPA1'
-- Equation name is 'data1', location is LC056, type is output.
data1 = TRI(SavedPA1, GLOBAL(!~PIN001));
SavedPA1 = DFFE( _EQ006 $ _EQ007, !ZHJS, VCC, VCC, VCC);
_EQ006 = !count1 & !count2 & !count3 & !CS & RD & tmpbitvector2
# CS & SavedPA1
# !RD & SavedPA1;
_EQ007 = count3 & !CS & RD & tmpbitvector2 & _X001;
_X001 = EXP(!count1 & !count2);
-- Node name is 'data2' = 'SavedPA2'
-- Equation name is 'data2', location is LC053, type is output.
data2 = TRI(SavedPA2, GLOBAL(!~PIN001));
SavedPA2 = DFFE( _EQ008 $ _EQ009, !ZHJS, VCC, VCC, VCC);
_EQ008 = !count1 & !count2 & !count3 & !CS & RD & tmpbitvector3
# CS & SavedPA2
# !RD & SavedPA2;
_EQ009 = count3 & !CS & RD & tmpbitvector3 & _X001;
_X001 = EXP(!count1 & !count2);
-- Node name is 'data3' = 'SavedPA3'
-- Equation name is 'data3', location is LC036, type is output.
data3 = TRI(SavedPA3, GLOBAL(!~PIN001));
SavedPA3 = DFFE( _EQ010 $ _EQ011, !ZHJS, VCC, VCC, VCC);
_EQ010 = !count1 & !count2 & !count3 & !CS & RD & tmpbitvector4
# CS & SavedPA3
# !RD & SavedPA3;
_EQ011 = count3 & !CS & RD & tmpbitvector4 & _X001;
_X001 = EXP(!count1 & !count2);
-- Node name is 'data4' = 'SavedPA4'
-- Equation name is 'data4', location is LC052, type is output.
data4 = TRI(SavedPA4, GLOBAL(!~PIN001));
SavedPA4 = DFFE( _EQ012 $ _EQ013, !ZHJS, VCC, VCC, VCC);
_EQ012 = !count1 & !count2 & !count3 & !CS & RD & tmpbitvector5
# CS & SavedPA4
# !RD & SavedPA4;
_EQ013 = count3 & !CS & RD & tmpbitvector5 & _X001;
_X001 = EXP(!count1 & !count2);
-- Node name is 'data5' = 'SavedPA5'
-- Equation name is 'data5', location is LC051, type is output.
data5 = TRI(SavedPA5, GLOBAL(!~PIN001));
SavedPA5 = DFFE( _EQ014 $ _EQ015, !ZHJS, VCC, VCC, VCC);
_EQ014 = !count1 & !count2 & !count3 & !CS & RD & tmpbitvector6
# CS & SavedPA5
# !RD & SavedPA5;
_EQ015 = count3 & !CS & RD & tmpbitvector6 & _X001;
_X001 = EXP(!count1 & !count2);
-- Node name is 'data6' = 'SavedPA6'
-- Equation name is 'data6', location is LC035, type is output.
data6 = TRI(SavedPA6, GLOBAL(!~PIN001));
SavedPA6 = DFFE( _EQ016 $ _EQ017, !ZHJS, VCC, VCC, VCC);
_EQ016 = !count1 & !count2 & !count3 & !CS & RD & tmpbitvector7
# CS & SavedPA6
# !RD & SavedPA6;
_EQ017 = count3 & !CS & RD & tmpbitvector7 & _X001;
_X001 = EXP(!count1 & !count2);
-- Node name is 'data7' = 'SavedPA7'
-- Equation name is 'data7', location is LC049, type is output.
data7 = TRI(SavedPA7, GLOBAL(!~PIN001));
SavedPA7 = DFFE( _EQ018 $ _EQ019, !ZHJS, VCC, VCC, VCC);
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -