📄 ps.rpt
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Project Information d:\maxplus2\maxplus2\example\ps.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 12/23/2008 09:42:14
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
PS
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
ps EPM7064LC44-7 5 19 0 33 3 51 %
User Pins: 4 18 0
Project Information d:\maxplus2\maxplus2\example\ps.rpt
** MULTIPLE PIN CONNECTIONS **
For node name '~905~2' (Same as node '~PIN001')
For node name '~905~1' (Same as node '~PIN002')
Connect: {ps@44, ps@27}
Project Information d:\maxplus2\maxplus2\example\ps.rpt
** FILE HIERARCHY **
|lpm_add_sub:693|
|lpm_add_sub:693|addcore:adder|
|lpm_add_sub:693|addcore:adder|addcore:adder0|
|lpm_add_sub:693|altshift:result_ext_latency_ffs|
|lpm_add_sub:693|altshift:carry_ext_latency_ffs|
|lpm_add_sub:693|altshift:oflow_ext_latency_ffs|
Device-Specific Information: d:\maxplus2\maxplus2\example\ps.rpt
ps
***** Logic for device 'ps' compiled without errors.
Device: EPM7064LC44-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
R R R
E E E ~
S S S P
E E E I
R R R N
V V V V G G 0 G G P P
E E E C N N 0 N N A A
D D D C D D 1 D D 4 7
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
RESERVED | 7 39 | PA5
k_data | 8 38 | data1
RD | 9 37 | data2
GND | 10 36 | data4
clk | 11 35 | VCC
CS | 12 EPM7064LC44-7 34 | data5
RESERVED | 13 33 | data7
RESERVED | 14 32 | PA6
VCC | 15 31 | INTR2
RESERVED | 16 30 | GND
RESERVED | 17 29 | PA3
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
R P P P G V Z d d ~ d
E A A A N C H a a P a
S 0 1 2 D C J t t I t
E S a a N a
R 6 3 0 0
V 0
E 2
D
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: d:\maxplus2\maxplus2\example\ps.rpt
ps
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 4/ 8( 50%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 3/16( 18%) 3/ 8( 37%) 0/16( 0%) 7/36( 19%)
C: LC33 - LC48 14/16( 87%) 8/ 8(100%) 5/16( 31%) 16/36( 44%)
D: LC49 - LC64 16/16(100%) 8/ 8(100%) 6/16( 37%) 22/36( 61%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 23/32 ( 71%)
Total logic cells used: 33/64 ( 51%)
Total shareable expanders used: 3/64 ( 4%)
Total Turbo logic cells used: 33/64 ( 51%)
Total shareable expanders not available (n/a): 8/64 ( 12%)
Average fan-in: 6.60
Total fan-in: 218
Total input pins required: 5
Total output pins required: 19
Total bidirectional pins required: 0
Total logic cells required: 33
Total flipflops required: 22
Total product terms required: 116
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 2
Synthesized logic cells: 0/ 64 ( 0%)
Device-Specific Information: d:\maxplus2\maxplus2\example\ps.rpt
ps
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
11 (3) (A) INPUT 0 0 0 0 0 1 12 clk
12 (1) (A) INPUT 0 0 0 0 0 19 12 CS
8 (5) (A) INPUT 0 0 0 0 0 0 8 k_data
44 - - INPUT G s 0 0 0 0 0 0 0 ~PIN001
9 (4) (A) INPUT 0 0 0 0 0 10 0 RD
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\maxplus2\maxplus2\example\ps.rpt
ps
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
28 40 C TRI/FF t 2 1 1 2 6 1 0 data0 (:45)
38 56 D TRI/FF t 2 1 1 2 6 1 0 data1 (:44)
37 53 D TRI/FF t 2 1 1 2 6 1 0 data2 (:43)
26 36 C TRI/FF t 2 1 1 2 6 1 0 data3 (:42)
36 52 D TRI/FF t 2 1 1 2 6 1 0 data4 (:41)
34 51 D TRI/FF t 2 1 1 2 6 1 0 data5 (:40)
25 35 C TRI/FF t 2 1 1 2 6 1 0 data6 (:39)
33 49 D TRI/FF t 2 1 1 2 6 1 0 data7 (:38)
31 46 C FF t 1 0 0 2 1 0 0 INTR2
19 20 B OUTPUT t 0 0 0 1 4 0 0 PA0
20 19 B OUTPUT t 0 0 0 1 4 0 0 PA1
21 17 B OUTPUT t 0 0 0 1 4 0 0 PA2
29 41 C OUTPUT t 0 0 0 1 4 0 0 PA3
41 64 D OUTPUT t 0 0 0 1 4 0 0 PA4
39 57 D OUTPUT t 0 0 0 1 4 0 0 PA5
32 48 C OUTPUT t 0 0 0 1 4 0 0 PA6
40 62 D OUTPUT t 0 0 0 1 4 0 0 PA7
27 37 C OUTPUT t 0 0 0 2 0 0 0 ~PIN002
24 33 C FF t 0 0 0 2 4 9 0 ZHJS
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\maxplus2\maxplus2\example\ps.rpt
ps
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 38 C SOFT t 0 0 0 0 3 0 1 |LPM_ADD_SUB:693|addcore:adder|addcore:adder0|result_node2
- 39 C SOFT t 0 0 0 0 4 0 1 |LPM_ADD_SUB:693|addcore:adder|addcore:adder0|result_node3
- 58 D TFFE t 0 0 0 3 5 2 1 tmpbitvector8 (:28)
- 55 D TFFE t 0 0 0 3 5 2 1 tmpbitvector7 (:29)
- 60 D TFFE t 0 0 0 3 5 2 1 tmpbitvector6 (:30)
- 54 D TFFE t 0 0 0 3 5 2 1 tmpbitvector5 (:31)
- 59 D TFFE t 0 0 0 3 5 2 1 tmpbitvector4 (:32)
- 61 D TFFE t 0 0 0 3 5 2 1 tmpbitvector3 (:33)
- 63 D TFFE t 0 0 0 3 5 2 1 tmpbitvector2 (:34)
- 50 D TFFE t 0 0 0 3 5 2 1 tmpbitvector1 (:35)
- 34 C DFFE t 0 0 0 2 5 17 12 count3 (:48)
- 42 C DFFE t 0 0 0 2 5 17 13 count2 (:49)
- 44 C TFFE t 0 0 0 2 1 17 13 count1 (:50)
- 43 C TFFE t 0 0 0 2 4 1 14 count0 (:51)
Code:
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