📄 tribuffer.rpt
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Device-Specific Information:e:\my documents\my_vhdl\sram_controller\tribuffer.rpt
tribuffer
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - B 23 LCELL s 1 0 1 0 ~164~1
- 8 - A 04 LCELL s 1 0 1 0 ~165~1
- 3 - B 13 LCELL s 1 0 1 0 ~166~1
- 7 - A 08 LCELL s 1 0 1 0 ~167~1
- 2 - A 22 LCELL s 1 0 1 0 ~168~1
- 1 - B 24 LCELL s 1 0 1 0 ~169~1
- 1 - C 05 LCELL s 1 0 1 0 ~170~1
- 2 - B 05 LCELL s 1 0 1 0 ~171~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\my documents\my_vhdl\sram_controller\tribuffer.rpt
tribuffer
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/ 96( 2%) 1/ 48( 2%) 1/ 48( 2%) 1/16( 6%) 3/16( 18%) 0/16( 0%)
B: 5/ 96( 5%) 0/ 48( 0%) 1/ 48( 2%) 2/16( 12%) 4/16( 25%) 0/16( 0%)
C: 0/ 96( 0%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\my documents\my_vhdl\sram_controller\tribuffer.rpt
tribuffer
** EQUATIONS **
datain0 : INPUT;
datain1 : INPUT;
datain2 : INPUT;
datain3 : INPUT;
datain4 : INPUT;
datain5 : INPUT;
datain6 : INPUT;
datain7 : INPUT;
oe : INPUT;
-- Node name is 'dataout0'
-- Equation name is 'dataout0', type is output
dataout0 = TRI(_LC2_B5, GLOBAL( oe));
-- Node name is 'dataout1'
-- Equation name is 'dataout1', type is output
dataout1 = TRI(_LC1_C5, GLOBAL( oe));
-- Node name is 'dataout2'
-- Equation name is 'dataout2', type is output
dataout2 = TRI(_LC1_B24, GLOBAL( oe));
-- Node name is 'dataout3'
-- Equation name is 'dataout3', type is output
dataout3 = TRI(_LC2_A22, GLOBAL( oe));
-- Node name is 'dataout4'
-- Equation name is 'dataout4', type is output
dataout4 = TRI(_LC7_A8, GLOBAL( oe));
-- Node name is 'dataout5'
-- Equation name is 'dataout5', type is output
dataout5 = TRI(_LC3_B13, GLOBAL( oe));
-- Node name is 'dataout6'
-- Equation name is 'dataout6', type is output
dataout6 = TRI(_LC8_A4, GLOBAL( oe));
-- Node name is 'dataout7'
-- Equation name is 'dataout7', type is output
dataout7 = TRI(_LC7_B23, GLOBAL( oe));
-- Node name is '~164~1'
-- Equation name is '~164~1', location is LC7_B23, type is buried.
-- synthesized logic cell
_LC7_B23 = LCELL( datain7);
-- Node name is '~165~1'
-- Equation name is '~165~1', location is LC8_A4, type is buried.
-- synthesized logic cell
_LC8_A4 = LCELL( datain6);
-- Node name is '~166~1'
-- Equation name is '~166~1', location is LC3_B13, type is buried.
-- synthesized logic cell
_LC3_B13 = LCELL( datain5);
-- Node name is '~167~1'
-- Equation name is '~167~1', location is LC7_A8, type is buried.
-- synthesized logic cell
_LC7_A8 = LCELL( datain4);
-- Node name is '~168~1'
-- Equation name is '~168~1', location is LC2_A22, type is buried.
-- synthesized logic cell
_LC2_A22 = LCELL( datain3);
-- Node name is '~169~1'
-- Equation name is '~169~1', location is LC1_B24, type is buried.
-- synthesized logic cell
_LC1_B24 = LCELL( datain2);
-- Node name is '~170~1'
-- Equation name is '~170~1', location is LC1_C5, type is buried.
-- synthesized logic cell
_LC1_C5 = LCELL( datain1);
-- Node name is '~171~1'
-- Equation name is '~171~1', location is LC2_B5, type is buried.
-- synthesized logic cell
_LC2_B5 = LCELL( datain0);
Project Information e:\my documents\my_vhdl\sram_controller\tribuffer.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,939K
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