📄 srm_read_and_write.rpt
字号:
65 - - B -- OUTPUT 0 1 0 0 Address6
24 - - B -- OUTPUT 0 1 0 0 Address7
62 - - C -- OUTPUT 0 1 0 0 Address8
21 - - B -- OUTPUT 0 1 0 0 Address9
39 - - - 11 OUTPUT 0 1 0 0 Address10
5 - - - 05 OUTPUT 0 1 0 0 CE
71 - - A -- OUTPUT 0 1 0 0 DATAout0
9 - - - 02 OUTPUT 0 1 0 0 DATAout1
30 - - C -- OUTPUT 0 1 0 0 DATAout2
22 - - B -- OUTPUT 0 1 0 0 DATAout3
28 - - C -- OUTPUT 0 1 0 0 DATAout4
37 - - - 09 OUTPUT 0 1 0 0 DATAout5
23 - - B -- OUTPUT 0 1 0 0 DATAout6
25 - - B -- OUTPUT 0 1 0 0 DATAout7
19 - - A -- TRI 0 1 0 1 memdata0
17 - - A -- TRI 0 1 0 1 memdata1
60 - - C -- TRI 0 1 0 1 memdata2
10 - - - 01 TRI 0 1 0 1 memdata3
18 - - A -- TRI 0 1 0 1 memdata4
27 - - C -- TRI 0 1 0 1 memdata5
38 - - - 10 TRI 0 1 0 1 memdata6
29 - - C -- TRI 0 1 0 1 memdata7
69 - - A -- OUTPUT 0 1 0 0 OE
11 - - - 01 OUTPUT 0 1 0 0 WE
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:e:\my documents\my_vhdl\sram_controller\srm_read_and_write.rpt
srm_read_and_write
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - B 17 AND2 0 2 0 3 |SRAMCONTROLLER:1|LPM_ADD_SUB:613|addcore:adder|:87
- 8 - B 17 AND2 0 2 0 3 |SRAMCONTROLLER:1|LPM_ADD_SUB:613|addcore:adder|:91
- 3 - B 15 AND2 0 2 0 3 |SRAMCONTROLLER:1|LPM_ADD_SUB:613|addcore:adder|:95
- 4 - B 15 AND2 0 2 0 3 |SRAMCONTROLLER:1|LPM_ADD_SUB:613|addcore:adder|:99
- 8 - B 15 AND2 0 2 0 3 |SRAMCONTROLLER:1|LPM_ADD_SUB:613|addcore:adder|:103
- 2 - B 19 AND2 0 2 0 3 |SRAMCONTROLLER:1|LPM_ADD_SUB:613|addcore:adder|:107
- 8 - B 19 AND2 0 2 0 3 |SRAMCONTROLLER:1|LPM_ADD_SUB:613|addcore:adder|:111
- 3 - B 12 AND2 0 2 0 3 |SRAMCONTROLLER:1|LPM_ADD_SUB:613|addcore:adder|:115
- 8 - B 12 AND2 0 2 0 5 |SRAMCONTROLLER:1|LPM_ADD_SUB:613|addcore:adder|:119
- 5 - C 09 DFFE + 1 2 1 0 |SRAMCONTROLLER:1|:18
- 2 - C 09 DFFE + 1 2 1 0 |SRAMCONTROLLER:1|:20
- 1 - C 09 DFFE + 1 2 1 0 |SRAMCONTROLLER:1|:22
- 5 - A 01 DFFE + 1 2 1 0 |SRAMCONTROLLER:1|:24
- 6 - A 01 DFFE + 1 2 1 0 |SRAMCONTROLLER:1|:26
- 4 - C 09 DFFE + 1 2 1 0 |SRAMCONTROLLER:1|:28
- 3 - A 01 DFFE + 1 2 1 0 |SRAMCONTROLLER:1|:30
- 7 - A 01 DFFE + 1 2 1 0 |SRAMCONTROLLER:1|:32
- 8 - C 09 DFFE + 0 3 1 0 |SRAMCONTROLLER:1|:34
- 3 - B 08 DFFE + 0 3 1 0 |SRAMCONTROLLER:1|:36
- 6 - C 09 DFFE + 0 3 1 0 |SRAMCONTROLLER:1|:38
- 3 - C 09 DFFE + 0 3 1 0 |SRAMCONTROLLER:1|:40
- 1 - B 08 DFFE + 0 3 1 0 |SRAMCONTROLLER:1|:42
- 7 - C 09 DFFE + 0 3 1 0 |SRAMCONTROLLER:1|:44
- 2 - A 01 DFFE + 0 3 1 0 |SRAMCONTROLLER:1|:46
- 4 - A 01 DFFE + 0 3 1 0 |SRAMCONTROLLER:1|:48
- 2 - B 12 DFFE + 0 3 1 3 |SRAMCONTROLLER:1|:50
- 1 - B 12 DFFE + 0 3 1 1 |SRAMCONTROLLER:1|:52
- 1 - B 19 DFFE + 0 3 1 1 |SRAMCONTROLLER:1|:54
- 6 - B 19 DFFE + 0 3 1 1 |SRAMCONTROLLER:1|:56
- 5 - B 19 DFFE + 0 3 1 1 |SRAMCONTROLLER:1|:58
- 2 - B 15 DFFE + 0 3 1 1 |SRAMCONTROLLER:1|:60
- 1 - B 15 DFFE + 0 3 1 1 |SRAMCONTROLLER:1|:62
- 6 - B 15 DFFE + 0 3 1 1 |SRAMCONTROLLER:1|:64
- 7 - B 17 DFFE + 0 3 1 1 |SRAMCONTROLLER:1|:66
- 3 - B 17 DFFE + 0 3 1 1 |SRAMCONTROLLER:1|:68
- 5 - B 17 DFFE + 0 1 1 3 |SRAMCONTROLLER:1|:70
- 2 - B 05 DFFE + 0 3 1 0 |SRAMCONTROLLER:1|:72
- 2 - B 02 DFFE + 0 3 0 8 |SRAMCONTROLLER:1|counter3 (|SRAMCONTROLLER:1|:76)
- 1 - B 02 DFFE + 0 2 0 9 |SRAMCONTROLLER:1|counter2 (|SRAMCONTROLLER:1|:77)
- 3 - B 02 DFFE + 0 3 0 8 |SRAMCONTROLLER:1|counter1 (|SRAMCONTROLLER:1|:78)
- 1 - B 04 DFFE + 0 0 0 9 |SRAMCONTROLLER:1|counter0 (|SRAMCONTROLLER:1|:79)
- 8 - A 01 DFFE +s 0 3 1 0 |SRAMCONTROLLER:1|read~1 (|SRAMCONTROLLER:1|~80~1)
- 1 - A 01 DFFE + 0 3 1 16 |SRAMCONTROLLER:1|read (|SRAMCONTROLLER:1|:80)
- 2 - B 08 OR2 s 0 2 0 1 |SRAMCONTROLLER:1|~267~1
- 6 - B 08 AND2 s 0 2 0 10 |SRAMCONTROLLER:1|~267~2
- 6 - B 02 AND2 0 4 0 9 |SRAMCONTROLLER:1|:267
- 7 - B 02 AND2 s 0 4 0 1 |SRAMCONTROLLER:1|~276~1
- 5 - B 02 OR2 ! 0 4 0 1 |SRAMCONTROLLER:1|:276
- 4 - B 12 AND2 0 4 0 2 |SRAMCONTROLLER:1|:303
- 6 - B 12 OR2 s 0 3 0 10 |SRAMCONTROLLER:1|~747~1
- 7 - B 12 OR2 s 0 3 0 1 |SRAMCONTROLLER:1|~770~1
- 5 - B 12 OR2 s 0 3 0 1 |SRAMCONTROLLER:1|~788~1
- 7 - B 19 OR2 s 0 3 0 1 |SRAMCONTROLLER:1|~806~1
- 4 - B 19 OR2 s 0 3 0 1 |SRAMCONTROLLER:1|~824~1
- 3 - B 19 OR2 s 0 3 0 1 |SRAMCONTROLLER:1|~842~1
- 7 - B 15 OR2 s 0 3 0 1 |SRAMCONTROLLER:1|~860~1
- 5 - B 15 OR2 s 0 3 0 1 |SRAMCONTROLLER:1|~878~1
- 2 - B 17 OR2 s 0 3 0 1 |SRAMCONTROLLER:1|~896~1
- 6 - B 17 OR2 s 0 3 0 1 |SRAMCONTROLLER:1|~914~1
- 4 - B 17 OR2 s 0 3 0 1 |SRAMCONTROLLER:1|~932~1
- 4 - B 02 AND2 s ! 0 4 0 13 |SRAMCONTROLLER:1|~950~1
- 8 - B 02 OR2 s 0 4 0 8 |SRAMCONTROLLER:1|~1112~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\my documents\my_vhdl\sram_controller\srm_read_and_write.rpt
srm_read_and_write
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 7/ 96( 7%) 7/ 48( 14%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 3/16( 18%)
B: 8/ 96( 8%) 16/ 48( 33%) 7/ 48( 14%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
C: 9/ 96( 9%) 6/ 48( 12%) 1/ 48( 2%) 3/16( 18%) 3/16( 18%) 3/16( 18%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 3/24( 12%) 0/4( 0%) 1/4( 25%) 1/4( 25%)
02: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 2/24( 8%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
11: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\my documents\my_vhdl\sram_controller\srm_read_and_write.rpt
srm_read_and_write
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 34 CLOCK
Device-Specific Information:e:\my documents\my_vhdl\sram_controller\srm_read_and_write.rpt
srm_read_and_write
** EQUATIONS **
CLOCK : INPUT;
DATAin0 : INPUT;
DATAin1 : INPUT;
DATAin2 : INPUT;
DATAin3 : INPUT;
DATAin4 : INPUT;
DATAin5 : INPUT;
DATAin6 : INPUT;
DATAin7 : INPUT;
-- Node name is 'Address0'
-- Equation name is 'Address0', type is output
Address0 = _LC5_B17;
-- Node name is 'Address1'
-- Equation name is 'Address1', type is output
Address1 = _LC3_B17;
-- Node name is 'Address2'
-- Equation name is 'Address2', type is output
Address2 = _LC7_B17;
-- Node name is 'Address3'
-- Equation name is 'Address3', type is output
Address3 = _LC6_B15;
-- Node name is 'Address4'
-- Equation name is 'Address4', type is output
Address4 = _LC1_B15;
-- Node name is 'Address5'
-- Equation name is 'Address5', type is output
Address5 = _LC2_B15;
-- Node name is 'Address6'
-- Equation name is 'Address6', type is output
Address6 = _LC5_B19;
-- Node name is 'Address7'
-- Equation name is 'Address7', type is output
Address7 = _LC6_B19;
-- Node name is 'Address8'
-- Equation name is 'Address8', type is output
Address8 = _LC1_B19;
-- Node name is 'Address9'
-- Equation name is 'Address9', type is output
Address9 = _LC1_B12;
-- Node name is 'Address10'
-- Equation name is 'Address10', type is output
Address10 = _LC2_B12;
-- Node name is 'CE'
-- Equation name is 'CE', type is output
CE = _LC2_B5;
-- Node name is 'DATAout0'
-- Equation name is 'DATAout0', type is output
DATAout0 = _LC4_A1;
-- Node name is 'DATAout1'
-- Equation name is 'DATAout1', type is output
DATAout1 = _LC2_A1;
-- Node name is 'DATAout2'
-- Equation name is 'DATAout2', type is output
DATAout2 = _LC7_C9;
-- Node name is 'DATAout3'
-- Equation name is 'DATAout3', type is output
DATAout3 = _LC1_B8;
-- Node name is 'DATAout4'
-- Equation name is 'DATAout4', type is output
DATAout4 = _LC3_C9;
-- Node name is 'DATAout5'
-- Equation name is 'DATAout5', type is output
DATAout5 = _LC6_C9;
-- Node name is 'DATAout6'
-- Equation name is 'DATAout6', type is output
DATAout6 = _LC3_B8;
-- Node name is 'DATAout7'
-- Equation name is 'DATAout7', type is output
DATAout7 = _LC8_C9;
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