lcd_top.syr

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Optimizing unit <lcd_top> ...
WARNING:Xst:1710 - FF/Latch  <display_dir_7> (without init value) has a constant value of 1 in block <lcd_top>.

Optimizing unit <lcd> ...

Mapping all equations...
WARNING:Xst:1710 - FF/Latch  <lcd/DDout_6> (without init value) has a constant value of 0 in block <lcd_top>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block lcd_top, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : lcd_top.ngr
Top Level Output File Name         : lcd_top
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 13

Cell Usage :
# BELS                             : 250
#      GND                         : 1
#      INV                         : 6
#      LUT1                        : 22
#      LUT1_L                      : 2
#      LUT2                        : 2
#      LUT2_L                      : 34
#      LUT3                        : 9
#      LUT3_L                      : 2
#      LUT4                        : 35
#      LUT4_L                      : 4
#      MULT_AND                    : 1
#      MUXCY                       : 69
#      MUXF5                       : 9
#      VCC                         : 1
#      XORCY                       : 53
# FlipFlops/Latches                : 78
#      FDC                         : 56
#      FDCE                        : 16
#      FDE                         : 4
#      FDPE                        : 1
#      FDSE                        : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 12
#      IBUF                        : 1
#      OBUF                        : 11
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                      60  out of   3584     1%  
 Number of Slice Flip Flops:            78  out of   7168     1%  
 Number of 4 input LUTs:               110  out of   7168     1%  
 Number of bonded IOBs:                 13  out of    141     9%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
Clk                                | BUFGP                  | 78    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 11.564ns (Maximum Frequency: 86.475MHz)
   Minimum input arrival time before clock: 4.107ns
   Maximum output required time after clock: 7.271ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'Clk'
  Clock period: 11.564ns (frequency: 86.475MHz)
  Total number of paths / destination ports: 17814 / 100
-------------------------------------------------------------------------
Delay:               11.564ns (Levels of Logic = 46)
  Source:            lcd/i_4 (FF)
  Destination:       lcd/i_31 (FF)
  Source Clock:      Clk rising
  Destination Clock: Clk rising

  Data Path: lcd/i_4 to lcd/i_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   0.720   1.216  lcd/i_4 (lcd/i_4)
     LUT1_L:I0->LO         1   0.551   0.000  lcd/i_4_rt (lcd/i_4_rt)
     MUXCY:S->O            1   0.500   0.000  lcd/Mcompar__n0008_andcy (lcd/Mcompar__n0008_and_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd/Mcompar__n0008_norcy (lcd/Mcompar__n0008_nor_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd/Mcompar__n0008_andcy_rn_0 (lcd/Mcompar__n0008_and_cyo1)
     MUXCY:CI->O           1   0.064   0.000  lcd/Mcompar__n0008_norcy_rn_0 (lcd/Mcompar__n0008_nor_cyo1)
     MUXCY:CI->O           1   0.064   0.000  lcd/Mcompar__n0008_andcy_rn_1 (lcd/Mcompar__n0008_and_cyo2)
     MUXCY:CI->O           1   0.064   0.000  lcd/Mcompar__n0008_norcy_rn_1 (lcd/Mcompar__n0008_nor_cyo2)
     MUXCY:CI->O           1   0.064   0.000  lcd/Mcompar__n0008_norcy_rn_2 (lcd/Mcompar__n0008_nor_cyo3)
     MUXCY:CI->O           1   0.064   0.000  lcd/Mcompar__n0008_norcy_rn_3 (lcd/Mcompar__n0008_nor_cyo4)
     MUXCY:CI->O           1   0.064   0.000  lcd/Mcompar__n0008_norcy_rn_4 (lcd/Mcompar__n0008_nor_cyo5)
     MUXCY:CI->O           1   0.064   0.000  lcd/Mcompar__n0008_norcy_rn_5 (lcd/Mcompar__n0008_nor_cyo6)
     MUXCY:CI->O          25   0.281   1.813  lcd/Mcompar__n0008_gecy (lcd/Mcompar__n0008_ge_cyo)
     INV:I->O              8   0.551   1.278  lcd/Mcompar__n0008_ge_cyo_INV_1_INV_0 (lcd/Mcompar__n0008_ge_cyo_INV)
     LUT2_L:I1->LO         2   0.551   0.000  lcd/lcd_Result<0>lut (lcd/Result<0>)
     MUXCY:S->O            1   0.500   0.000  lcd/lcd_Result<0>cy (lcd/lcd_Result<0>_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd/lcd_Result<1>cy (lcd/lcd_Result<1>_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd/lcd_Result<2>cy (lcd/lcd_Result<2>_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd/lcd_Result<3>cy (lcd/lcd_Result<3>_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd/lcd_Result<4>cy (lcd/lcd_Result<4>_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd/lcd_Result<5>cy (lcd/lcd_Result<5>_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd/lcd_Result<6>cy (lcd/lcd_Result<6>_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd/lcd_Result<7>cy (lcd/lcd_Result<7>_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd/lcd_Result<8>cy (lcd/lcd_Result<8>_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd/lcd_Result<9>cy (lcd/lcd_Result<9>_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd/lcd_Result<10>cy (lcd/lcd_Result<10>_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd/lcd_Result<11>cy (lcd/lcd_Result<11>_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd/lcd_Result<12>cy (lcd/lcd_Result<12>_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd/lcd_Result<13>cy (lcd/lcd_Result<13>_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd/lcd_Result<14>cy (lcd/lcd_Result<14>_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd/lcd_Result<15>cy (lcd/lcd_Result<15>_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd/lcd_Result<16>cy (lcd/lcd_Result<16>_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd/lcd_Result<17>cy (lcd/lcd_Result<17>_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd/lcd_Result<18>cy (lcd/lcd_Result<18>_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd/lcd_Result<19>cy (lcd/lcd_Result<19>_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd/lcd_Result<20>cy (lcd/lcd_Result<20>_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd/lcd_Result<21>cy (lcd/lcd_Result<21>_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd/lcd_Result<22>cy (lcd/lcd_Result<22>_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd/lcd_Result<23>cy (lcd/lcd_Result<23>_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd/lcd_Result<24>cy (lcd/lcd_Result<24>_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd/lcd_Result<25>cy (lcd/lcd_Result<25>_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd/lcd_Result<26>cy (lcd/lcd_Result<26>_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd/lcd_Result<27>cy (lcd/lcd_Result<27>_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd/lcd_Result<28>cy (lcd/lcd_Result<28>_cyo)
     MUXCY:CI->O           1   0.064   0.000  lcd/lcd_Result<29>cy (lcd/lcd_Result<29>_cyo)
     MUXCY:CI->O           0   0.064   0.000  lcd/lcd_Result<30>cy (lcd/lcd_Result<30>_cyo)
     XORCY:CI->O           1   0.904   0.000  lcd/lcd_Result<31>_xor (lcd/Result<31>)
     FDC:D                     0.203          lcd/i_31
    ----------------------------------------
    Total                     11.564ns (7.257ns logic, 4.307ns route)
                                       (62.8% logic, 37.2% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Clk'
  Total number of paths / destination ports: 4 / 4
-------------------------------------------------------------------------
Offset:              4.107ns (Levels of Logic = 2)
  Source:            Rst (PAD)
  Destination:       lcd/zstate_0 (FF)
  Destination Clock: Clk rising

  Data Path: Rst to lcd/zstate_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   0.821   1.216  Rst_IBUF (Rst_IBUF)
     LUT2:I0->O            4   0.551   0.917  lcd/_n00011 (lcd/_n0001)
     FDE:CE                    0.602          lcd/zstate_0
    ----------------------------------------
    Total                      4.107ns (1.974ns logic, 2.133ns route)
                                       (48.1% logic, 51.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk'
  Total number of paths / destination ports: 9 / 9
-------------------------------------------------------------------------
Offset:              7.271ns (Levels of Logic = 1)
  Source:            lcd/E (FF)
  Destination:       EN (PAD)
  Source Clock:      Clk rising

  Data Path: lcd/E to EN
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDPE:C->Q             3   0.720   0.907  lcd/E (lcd/E)
     OBUF:I->O                 5.644          EN_OBUF (EN)
    ----------------------------------------
    Total                      7.271ns (6.364ns logic, 0.907ns route)
                                       (87.5% logic, 12.5% route)

=========================================================================
CPU : 9.06 / 10.05 s | Elapsed : 9.00 / 10.00 s
 
--> 

Total memory usage is 114492 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    8 (   0 filtered)
Number of infos    :    3 (   0 filtered)