lcd_top.syr

本实例是学习fpga的入门程序 希望大家喜欢

Release 8.1i - xst I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.89 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.89 s | Elapsed : 0.00 / 1.00 s
 
--> Reading design: lcd_top.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
     5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "lcd_top.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "lcd_top"
Output Format                      : NGC
Target Device                      : xc3s400-4-pq208

---- Source Options
Top Module Name                    : lcd_top
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
RTL Output                         : Yes
Global Optimization                : AllClockNets
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : lcd_top.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "D:/Xilinx/disk1/medule/lcd.v" in library work
Compiling verilog file "lcd_top.v" in library work
Module <lcd> compiled
Module <lcd_top> compiled
No errors in compilation
Analysis of file <"lcd_top.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <lcd_top>.
Module <lcd_top> is correct for synthesis.
 
Analyzing module <lcd>.
	s0 = 32'sb00000000000000000000000000000000
	s1 = 32'sb00000000000000000000000000000001
	s2 = 32'sb00000000000000000000000000000010
	s3 = 32'sb00000000000000000000000000000011
	s4 = 32'sb00000000000000000000000000000100
	s5 = 32'sb00000000000000000000000000000101
	s6 = 32'sb00000000000000000000000000000110
	s7 = 32'sb00000000000000000000000000000111
	s8 = 32'sb00000000000000000000000000001000
	s9 = 32'sb00000000000000000000000000001001
	s10 = 32'sb00000000000000000000000000001010
	s11 = 32'sb00000000000000000000000000001011
	s12 = 32'sb00000000000000000000000000001100
	s13 = 32'sb00000000000000000000000000001101
	s14 = 32'sb00000000000000000000000000001110
	s15 = 32'sb00000000000000000000000000001111
Module <lcd> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================
INFO:Xst:1304 - Contents of register <num> in unit <lcd_top> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <RW> in unit <lcd> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <DelayT> in unit <lcd> never changes during circuit operation. The register is replaced by logic.

Synthesizing Unit <lcd>.
    Related source file is "D:/Xilinx/disk1/medule/lcd.v".
WARNING:Xst:1780 - Signal <char_dir> is never used or assigned.
    Found 8-bit register for signal <DDout>.
    Found 1-bit register for signal <E>.
    Found 1-bit register for signal <RS>.
    Found 33-bit comparator less for signal <$n0008> created at line 72.
    Found 32-bit up counter for signal <i>.
    Found 1-bit register for signal <start>.
    Found 4-bit register for signal <state>.
    Found 4-bit register for signal <zstate>.
    Summary:
	inferred   1 Counter(s).
	inferred  19 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <lcd> synthesized.


Synthesizing Unit <lcd_top>.
    Related source file is "lcd_top.v".
WARNING:Xst:646 - Signal <num10> is assigned but never used.
WARNING:Xst:646 - Signal <num1> is assigned but never used.
    Found 23-bit up counter for signal <display_cnt>.
    Found 8-bit register for signal <display_dir>.
    Found 1-bit register for signal <display_start>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <lcd_top> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                                             : 2
 23-bit up counter                                     : 1
 32-bit up counter                                     : 1
# Registers                                            : 8
 1-bit register                                        : 4
 4-bit register                                        : 2
 8-bit register                                        : 2
# Comparators                                          : 1
 33-bit comparator less                                : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Counters                                             : 2
 23-bit up counter                                     : 1
 32-bit up counter                                     : 1
# Registers                                            : 28
 Flip-Flops                                            : 28
# Comparators                                          : 1
 33-bit comparator less                                : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <display_dir_4> (without init value) has a constant value of 0 in block <lcd_top>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <display_dir_5> (without init value) has a constant value of 0 in block <lcd_top>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <display_dir_6> (without init value) has a constant value of 0 in block <lcd_top>.
Loading device for application Rf_Device from file '3s400.nph' in environment D:\Xilinx.