lcd_top.twr

本实例是学习fpga的入门程序 希望大家喜欢

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Release 8.1i Trace I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D:\Xilinx\bin\nt\trce.exe -ise lcdtest.ise -intstyle ise -e 3 -l 3 -s 4 -xml
lcd_top lcd_top.ncd -o lcd_top.twr lcd_top.pcf


Design file:              lcd_top.ncd
Physical constraint file: lcd_top.pcf
Device,speed:             xc3s400,-4 (PRODUCTION 1.37 2005-11-04)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock Clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
Rst         |    5.003(R)|   -1.644(R)|Clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock Clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
DB<0>       |    9.192(R)|Clk_BUFGP         |   0.000|
DB<1>       |    9.275(R)|Clk_BUFGP         |   0.000|
DB<2>       |    9.174(R)|Clk_BUFGP         |   0.000|
DB<3>       |    9.434(R)|Clk_BUFGP         |   0.000|
DB<4>       |    8.455(R)|Clk_BUFGP         |   0.000|
DB<5>       |    9.153(R)|Clk_BUFGP         |   0.000|
DB<7>       |    9.119(R)|Clk_BUFGP         |   0.000|
EN          |    9.485(R)|Clk_BUFGP         |   0.000|
RS          |    9.570(R)|Clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock Clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
Clk            |   10.113|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Wed Aug 01 21:38:37 2007
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Peak Memory Usage: 106 MB