gray1.vhd

几个VHDL实现的源程序及其代码

library ieee;
use ieee.std_logic_1164.all;

entity gray1 is
port(
g0,g1,g2,g3 : in std_logic; 
b0,b1,b2,b3 : OUT std_logic);
end gray1;

architecture behav of gray1 is
signal da : std_logic_vector(3 downto 0);
begin
b3<=g3;
b2<=((not g3) and g2) or (g3 and (not g2));
b1<=((not g3) and (not g2) and g1) or ((not g3) and g2 and (not g1)) or (g3 and (not g2) and (not g1));
b0<=((not g3) and (not g2) and (not g1) and g0) or ((not g3) and (not g2) and g1 and (not g0)) or ((not g3) and g2 and g1 and g0) or ((not g3) and g2 and (not g1) and (not g0)) or (g3 and g2 and (not g1) and g0) or (g3 and g2 and g1 and (not g0)) or (g3 and (not g2) and g1 and g0) or (g3 and (not g2) and (not g1) and (not g0));
end behav;