gray2.vhd

几个VHDL实现的源程序及其代码

library ieee;
use ieee.std_logic_1164.all;

entity gray2 is
port(
G : in std_logic_vector(3 downto 0); 
B : OUT std_logic_vector(3 downto 0));
end gray2;

architecture behav of gray2 is
begin
process(G)
begin
case G is
when "0000"=>B<="0000"; 
when "0001"=>B<="0001"; 
when "0010"=>B<="0011"; 
when "0011"=>B<="0010"; 
when "0100"=>B<="0111"; 
when "0101"=>B<="0110"; 
when "0110"=>B<="0100"; 
when "0111"=>B<="0101"; 
when "1000"=>B<="1111"; 
when "1001"=>B<="1110"; 
when "1010"=>B<="1100"; 
when "1011"=>B<="1101"; 
when "1100"=>B<="1000"; 
when "1101"=>B<="1001"; 
when "1110"=>B<="1001"; 
when "1111"=>B<="1000"; 
when others=>B<="XXXX";
END CASE;
END PROCESS;
END BEHAV;