📄 gray2.rpt
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IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - C 12 AND2 0 4 1 0 :391
- 7 - C 12 OR2 s ! 3 0 0 1 ~425~1
- 3 - C 12 OR2 s 3 0 0 2 ~439~1
- 4 - C 12 AND2 s ! 3 0 0 2 ~439~2
- 2 - C 08 OR2 2 0 1 0 :439
- 5 - C 12 AND2 3 0 0 1 :472
- 2 - C 12 AND2 s 3 0 0 2 ~479~1
- 8 - C 12 OR2 0 4 1 0 :487
- 6 - C 12 OR2 4 0 1 0 :535
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\windows\desktop\edaplay\test2\gray2\gray2.rpt
gray2
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 4/ 96( 4%) 4/ 48( 8%) 0/ 48( 0%) 3/16( 18%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\windows\desktop\edaplay\test2\gray2\gray2.rpt
gray2
** EQUATIONS **
G0 : INPUT;
G1 : INPUT;
G2 : INPUT;
G3 : INPUT;
-- Node name is 'B0'
-- Equation name is 'B0', type is output
B0 = _LC6_C12;
-- Node name is 'B1'
-- Equation name is 'B1', type is output
B1 = _LC8_C12;
-- Node name is 'B2'
-- Equation name is 'B2', type is output
B2 = _LC2_C8;
-- Node name is 'B3'
-- Equation name is 'B3', type is output
B3 = _LC1_C12;
-- Node name is ':391'
-- Equation name is '_LC1_C12', type is buried
_LC1_C12 = LCELL( _EQ001);
_EQ001 = !_LC2_C12 & _LC3_C12 & _LC4_C12 & !_LC7_C12;
-- Node name is '~425~1'
-- Equation name is '~425~1', location is LC7_C12, type is buried.
-- synthesized logic cell
!_LC7_C12 = _LC7_C12~NOT;
_LC7_C12~NOT = LCELL( _EQ002);
_EQ002 = G3
# !G2
# !G1;
-- Node name is '~439~1'
-- Equation name is '~439~1', location is LC3_C12, type is buried.
-- synthesized logic cell
_LC3_C12 = LCELL( _EQ003);
_EQ003 = G2
# G1
# G3;
-- Node name is '~439~2'
-- Equation name is '~439~2', location is LC4_C12, type is buried.
-- synthesized logic cell
!_LC4_C12 = _LC4_C12~NOT;
_LC4_C12~NOT = LCELL( _EQ004);
_EQ004 = G1 & !G2 & !G3;
-- Node name is ':439'
-- Equation name is '_LC2_C8', type is buried
_LC2_C8 = LCELL( _EQ005);
_EQ005 = G2 & !G3
# !G2 & G3;
-- Node name is ':472'
-- Equation name is '_LC5_C12', type is buried
_LC5_C12 = LCELL( _EQ006);
_EQ006 = !G1 & !G2 & G3;
-- Node name is '~479~1'
-- Equation name is '~479~1', location is LC2_C12, type is buried.
-- synthesized logic cell
_LC2_C12 = LCELL( _EQ007);
_EQ007 = !G1 & G2 & !G3;
-- Node name is ':487'
-- Equation name is '_LC8_C12', type is buried
_LC8_C12 = LCELL( _EQ008);
_EQ008 = _LC2_C12 & _LC3_C12
# _LC3_C12 & !_LC4_C12
# _LC3_C12 & _LC5_C12;
-- Node name is ':535'
-- Equation name is '_LC6_C12', type is buried
_LC6_C12 = LCELL( _EQ009);
_EQ009 = !G0 & G1 & !G2 & !G3
# G0 & !G1 & !G2 & !G3
# !G0 & !G1 & G2 & !G3
# !G0 & !G1 & !G2 & G3
# G0 & G1 & G2 & !G3
# G0 & G1 & !G2 & G3
# !G0 & G1 & G2 & G3
# G0 & !G1 & G2 & G3;
Project Information c:\windows\desktop\edaplay\test2\gray2\gray2.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 10,860K
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