📄 trafic.rpt
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_LC8_B8 = LCELL( _EQ016);
_EQ016 = _LC1_B6 & _LC2_B4 & _LC2_B6 & _LC4_B8;
-- Node name is '|T10:1|sx:l_d|~458~1'
-- Equation name is '_LC7_B15', type is buried
-- synthesized logic cell
_LC7_B15 = LCELL( _EQ017);
_EQ017 = _LC2_B4 & !_LC2_B6
# _LC1_B6 & _LC2_B4
# _LC2_B4 & _LC4_B8
# !_LC1_B6 & !_LC2_B6 & !_LC4_B8
# _LC1_B6 & _LC2_B6 & !_LC4_B8
# !_LC1_B6 & _LC2_B6 & _LC4_B8
# _LC1_B6 & !_LC2_B6 & _LC4_B8;
-- Node name is '|T10:1|sx:l_d|:498'
-- Equation name is '_LC7_B8', type is buried
_LC7_B8 = LCELL( _EQ018);
_EQ018 = _LC2_B4 & !_LC2_B6 & _LC4_B8
# _LC1_B6 & _LC2_B4 & !_LC4_B8
# _LC1_B6 & _LC2_B4 & !_LC2_B6
# _LC2_B4 & _LC2_B6 & !_LC4_B8;
-- Node name is '|T10:1|sx:l_d|:552'
-- Equation name is '_LC4_B4', type is buried
_LC4_B4 = LCELL( _EQ019);
_EQ019 = !_LC1_B6 & !_LC2_B4 & !_LC4_B8
# _LC2_B6 & !_LC4_B8
# _LC2_B4 & !_LC2_B6 & _LC4_B8
# _LC1_B6 & _LC2_B4
# !_LC1_B6 & !_LC2_B4 & _LC2_B6
# _LC1_B6 & !_LC2_B6 & _LC4_B8;
-- Node name is '|T10:1|sx:l_d|:599'
-- Equation name is '_LC7_B6', type is buried
_LC7_B6 = LCELL( _EQ020);
_EQ020 = !_LC2_B4
# !_LC2_B6 & !_LC4_B8
# !_LC1_B6 & !_LC2_B6
# _LC1_B6 & _LC2_B6
# _LC1_B6 & !_LC4_B8
# _LC2_B6 & _LC4_B8
# !_LC1_B6 & _LC4_B8;
-- Node name is '|T10:1|sx:l_d|~627~1'
-- Equation name is '_LC3_B6', type is buried
-- synthesized logic cell
_LC3_B6 = LCELL( _EQ021);
_EQ021 = _LC1_B6 & !_LC2_B6 & !_LC4_B8
# !_LC1_B6 & _LC2_B6 & !_LC4_B8
# _LC2_B4 & !_LC2_B6 & !_LC4_B8
# !_LC1_B6 & _LC2_B4 & !_LC4_B8;
-- Node name is '|T10:1|sx:l_d|~627~2'
-- Equation name is '_LC5_B10', type is buried
-- synthesized logic cell
_LC5_B10 = LCELL( _EQ022);
_EQ022 = _LC1_B6 & _LC2_B6 & !_LC4_B8;
-- Node name is '|T10:1|sx:l_d|:638'
-- Equation name is '_LC7_B10', type is buried
_LC7_B10 = LCELL( _EQ023);
_EQ023 = !_LC2_B10 & _LC5_B10
# !_LC2_B10 & _LC6_B10
# !_LC2_B10 & _LC3_B6;
-- Node name is '|T10:1|sx:l_d|~648~1'
-- Equation name is '_LC3_B15', type is buried
-- synthesized logic cell
!_LC3_B15 = _LC3_B15~NOT;
_LC3_B15~NOT = LCELL( _EQ024);
_EQ024 = !_LC1_B8 & !_LC8_B8;
-- Node name is '|T10:1|sx:l_d|:648'
-- Equation name is '_LC4_B10', type is buried
_LC4_B10 = LCELL( _EQ025);
_EQ025 = _LC7_B10
# _LC3_B15
# _LC3_B10
# _LC8_B15;
-- Node name is '|T10:1|sx:l_d|~681~1'
-- Equation name is '_LC2_B10', type is buried
-- synthesized logic cell
_LC2_B10 = LCELL( _EQ026);
_EQ026 = !_LC1_B6 & !_LC2_B4 & _LC2_B6 & _LC4_B8
# !_LC1_B6 & _LC2_B4 & !_LC2_B6 & _LC4_B8;
-- Node name is '|T10:1|sx:l_d|~681~2'
-- Equation name is '_LC5_B8', type is buried
-- synthesized logic cell
_LC5_B8 = LCELL( _EQ027);
_EQ027 = _LC4_B8
# _LC2_B6
# _LC1_B6 & _LC2_B4
# !_LC1_B6 & !_LC2_B4;
-- Node name is '|T10:1|sx:l_d|:690'
-- Equation name is '_LC1_B10', type is buried
_LC1_B10 = LCELL( _EQ028);
_EQ028 = _LC2_B10 & !_LC3_B10
# !_LC3_B10 & _LC5_B8
# _LC8_B15;
-- Node name is '|T10:1|sx:l_d|:706'
-- Equation name is '_LC6_B15', type is buried
_LC6_B15 = LCELL( _EQ029);
_EQ029 = !_LC3_B15 & !_LC4_B1 & _LC8_B15
# _LC2_B15 & !_LC3_B15 & !_LC4_B1;
-- Node name is '|T10:1|sx:l_d|:712'
-- Equation name is '_LC4_B15', type is buried
_LC4_B15 = LCELL( _EQ030);
_EQ030 = !_LC4_B1 & _LC7_B15 & !_LC8_B15
# !_LC4_B1 & _LC8_B8;
-- Node name is '|T10:1|sx:l_d|:718'
-- Equation name is '_LC2_B8', type is buried
_LC2_B8 = LCELL( _EQ031);
_EQ031 = !_LC1_B8 & !_LC4_B1 & _LC7_B8
# !_LC4_B1 & _LC8_B8;
-- Node name is '|T10:1|sx:l_d|:724'
-- Equation name is '_LC1_B4', type is buried
_LC1_B4 = LCELL( _EQ032);
_EQ032 = !_LC4_B1 & _LC4_B4;
-- Node name is '|T10:1|sx:l_d|:729'
-- Equation name is '_LC6_B6', type is buried
_LC6_B6 = LCELL( _EQ033);
_EQ033 = _LC4_B1 & _LC4_B6
# !_LC4_B1 & _LC7_B6
# _LC3_B15 & !_LC4_B1;
-- Node name is '|T10:1|sx:l_d|:735'
-- Equation name is '_LC5_B1', type is buried
_LC5_B1 = LCELL( _EQ034);
_EQ034 = !_LC4_B1 & _LC4_B10
# _LC4_B1 & _LC4_B6;
-- Node name is '|T10:1|sx:l_d|~737~1'
-- Equation name is '_LC4_B6', type is buried
-- synthesized logic cell
_LC4_B6 = LCELL( _EQ035);
_EQ035 = _LC3_B6
# !_LC2_B4 & !_LC4_B8 & _LC5_B6;
-- Node name is '|T10:1|sx:l_d|:742'
-- Equation name is '_LC3_B1', type is buried
_LC3_B1 = LCELL( _EQ036);
_EQ036 = !_LC1_B8 & _LC1_B10 & !_LC4_B1
# !_LC4_B1 & _LC8_B8;
-- Node name is '|T10:1|tbjsa:l_a|n_jk'
-- Equation name is '_LC6_B8', type is buried
_LC6_B8 = DFFE( _EQ037, GLOBAL( clk), VCC, VCC, VCC);
_EQ037 = _LC6_B8 & !_LC8_B8
# !_LC6_B8 & _LC8_B8;
-- Node name is '|T10:1|tbjsa:l_a|n_jk~1'
-- Equation name is '_LC4_B12', type is buried
-- synthesized logic cell
_LC4_B12 = DFFE( _EQ038, GLOBAL( clk), VCC, VCC, VCC);
_EQ038 = _LC4_B12 & !_LC8_B8
# !_LC4_B12 & _LC8_B8;
-- Node name is '|T10:1|tbjsa:l_a|n_jk~2'
-- Equation name is '_LC1_B15', type is buried
-- synthesized logic cell
_LC1_B15 = DFFE( _EQ039, GLOBAL( clk), VCC, VCC, VCC);
_EQ039 = _LC1_B15 & !_LC8_B8
# !_LC1_B15 & _LC8_B8;
-- Node name is '|T10:1|tbjsa:l_a|n_jk~3'
-- Equation name is '_LC5_B15', type is buried
-- synthesized logic cell
_LC5_B15 = DFFE( _EQ040, GLOBAL( clk), VCC, VCC, VCC);
_EQ040 = _LC5_B15 & !_LC8_B8
# !_LC5_B15 & _LC8_B8;
-- Node name is '|T10:1|tbjsa:l_a|n_jk~45'
-- Equation name is '_LC4_B8', type is buried
_LC4_B8 = DFFE( _EQ041, GLOBAL( clk), VCC, VCC, VCC);
_EQ041 = !_LC2_B6 & _LC4_B8
# !_LC2_B4 & _LC4_B8
# !_LC1_B6 & _LC4_B8
# _LC1_B6 & _LC2_B4 & _LC2_B6 & !_LC4_B8;
-- Node name is '|T10:1|tbjsa:l_a|n_jk~71'
-- Equation name is '_LC1_B6', type is buried
_LC1_B6 = DFFE( _EQ042, GLOBAL( clk), VCC, VCC, VCC);
_EQ042 = _LC1_B6 & !_LC2_B6
# _LC1_B6 & !_LC2_B4
# !_LC1_B6 & _LC2_B4 & _LC2_B6;
-- Node name is '|T10:1|tbjsa:l_a|n_jk~90'
-- Equation name is '_LC2_B6', type is buried
_LC2_B6 = DFFE( _EQ043, GLOBAL( clk), VCC, VCC, VCC);
_EQ043 = !_LC2_B4 & _LC2_B6
# _LC2_B4 & !_LC2_B6;
-- Node name is '|T10:1|tbjsa:l_a|n_jk~109'
-- Equation name is '_LC2_B4', type is buried
_LC2_B4 = DFFE(!_LC2_B4, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is '|T10:1|tbjsb:l_b|n_jk'
-- Equation name is '_LC2_B1', type is buried
_LC2_B1 = DFFE( _EQ044, GLOBAL( ckdsp), VCC, VCC, VCC);
_EQ044 = _LC2_B1 & !_LC4_B1
# !_LC2_B1 & _LC4_B1;
-- Node name is '|T10:1|tbjsb:l_b|n_jk~1'
-- Equation name is '_LC3_B4', type is buried
-- synthesized logic cell
_LC3_B4 = LCELL( _EQ045);
_EQ045 = !_LC2_B1 & _LC4_B1;
-- Node name is '|T10:1|tbjsb:l_b|n_jk~2'
-- Equation name is '_LC8_B1', type is buried
-- synthesized logic cell
_LC8_B1 = LCELL( _EQ046);
_EQ046 = _LC2_B1 & !_LC4_B1;
-- Node name is '|T10:1|tbjsb:l_b|n_jk~41'
-- Equation name is '_LC4_B1', type is buried
_LC4_B1 = DFFE(!_LC4_B1, GLOBAL( ckdsp), VCC, VCC, VCC);
-- Node name is '|74138:30|:15' = '|74138:30|Y0N'
-- Equation name is '_LC4_B5', type is buried
!_LC4_B5 = _LC4_B5~NOT;
_LC4_B5~NOT = LCELL( _EQ047);
_EQ047 = !_LC2_B1 & !_LC4_B1;
-- Node name is '|74138:30|:20' = '|74138:30|Y5N'
-- Equation name is '_LC1_B1', type is buried
!_LC1_B1 = _LC1_B1~NOT;
_LC1_B1~NOT = LCELL( _EQ048);
_EQ048 = _LC2_B1 & _LC4_B1;
Project Information d:\edaplay\digital\test11\trafic.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,112K
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