📄 trafic.rpt
字号:
- 7 - B 09 AND2 s 0 2 1 0 |T10:1|dk:l_c|~221~1
- 5 - B 13 AND2 0 2 1 0 |T10:1|dk:l_c|:221
- 2 - B 09 AND2 s 0 4 1 0 |T10:1|dk:l_c|~261~1
- 3 - B 08 AND2 0 4 1 0 |T10:1|dk:l_c|:261
- 8 - B 06 AND2 s 0 4 1 0 |T10:1|dk:l_c|~301~1
- 1 - B 16 AND2 0 4 1 0 |T10:1|dk:l_c|:301
- 6 - B 10 AND2 0 4 0 1 |T10:1|sx:l_d|:321
- 3 - B 10 OR2 ! 0 4 0 2 |T10:1|sx:l_d|:357
- 8 - B 15 AND2 s 0 3 0 4 |T10:1|sx:l_d|~384~1
- 2 - B 15 OR2 s 0 4 0 1 |T10:1|sx:l_d|~384~2
- 1 - B 08 OR2 ! 0 4 0 3 |T10:1|sx:l_d|:393
- 8 - B 08 AND2 0 4 0 8 |T10:1|sx:l_d|:405
- 7 - B 15 OR2 s 0 4 0 1 |T10:1|sx:l_d|~458~1
- 7 - B 08 OR2 0 4 0 1 |T10:1|sx:l_d|:498
- 4 - B 04 OR2 0 4 0 1 |T10:1|sx:l_d|:552
- 7 - B 06 OR2 0 4 0 1 |T10:1|sx:l_d|:599
- 3 - B 06 OR2 s 0 4 0 2 |T10:1|sx:l_d|~627~1
- 5 - B 10 AND2 s 0 3 0 1 |T10:1|sx:l_d|~627~2
- 7 - B 10 OR2 0 4 0 1 |T10:1|sx:l_d|:638
- 3 - B 15 AND2 s ! 0 2 0 3 |T10:1|sx:l_d|~648~1
- 4 - B 10 OR2 0 4 0 1 |T10:1|sx:l_d|:648
- 2 - B 10 OR2 s 0 4 0 2 |T10:1|sx:l_d|~681~1
- 5 - B 08 OR2 s 0 4 0 1 |T10:1|sx:l_d|~681~2
- 1 - B 10 OR2 0 4 0 1 |T10:1|sx:l_d|:690
- 6 - B 15 OR2 0 4 1 0 |T10:1|sx:l_d|:706
- 4 - B 15 OR2 0 4 1 0 |T10:1|sx:l_d|:712
- 2 - B 08 OR2 0 4 1 0 |T10:1|sx:l_d|:718
- 1 - B 04 AND2 0 2 1 0 |T10:1|sx:l_d|:724
- 6 - B 06 OR2 0 4 1 0 |T10:1|sx:l_d|:729
- 5 - B 01 OR2 0 3 1 0 |T10:1|sx:l_d|:735
- 4 - B 06 OR2 s 0 4 0 2 |T10:1|sx:l_d|~737~1
- 3 - B 01 OR2 0 4 1 0 |T10:1|sx:l_d|:742
- 6 - B 08 DFFE + 0 1 1 8 |T10:1|tbjsa:l_a|n_jk
- 4 - B 12 DFFE +s 0 1 1 0 |T10:1|tbjsa:l_a|n_jk~1
- 1 - B 15 DFFE +s 0 1 1 0 |T10:1|tbjsa:l_a|n_jk~2
- 5 - B 15 DFFE +s 0 1 1 0 |T10:1|tbjsa:l_a|n_jk~3
- 4 - B 08 DFFE + 0 3 0 20 |T10:1|tbjsa:l_a|n_jk~45
- 1 - B 06 DFFE + 0 2 0 21 |T10:1|tbjsa:l_a|n_jk~71
- 2 - B 06 DFFE + 0 1 0 22 |T10:1|tbjsa:l_a|n_jk~90
- 2 - B 04 DFFE + 0 0 0 16 |T10:1|tbjsa:l_a|n_jk~109
- 2 - B 01 DFFE + 0 1 0 4 |T10:1|tbjsb:l_b|n_jk
- 3 - B 04 AND2 s 0 2 1 0 |T10:1|tbjsb:l_b|n_jk~1
- 8 - B 01 AND2 s 0 2 1 0 |T10:1|tbjsb:l_b|n_jk~2
- 4 - B 01 DFFE + 0 0 0 12 |T10:1|tbjsb:l_b|n_jk~41
- 4 - B 05 AND2 ! 0 2 1 0 |74138:30|Y0N (|74138:30|:15)
- 1 - B 01 AND2 ! 0 2 1 0 |74138:30|Y5N (|74138:30|:20)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\edaplay\digital\test11\trafic.rpt
trafic
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 3/ 48( 6%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 14/ 96( 14%) 11/ 48( 22%) 0/ 48( 0%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
C: 1/ 96( 1%) 3/ 48( 6%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\edaplay\digital\test11\trafic.rpt
trafic
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 9 clk
INPUT 2 ckdsp
Device-Specific Information: d:\edaplay\digital\test11\trafic.rpt
trafic
** EQUATIONS **
ckdsp : INPUT;
clk : INPUT;
-- Node name is 'D0'
-- Equation name is 'D0', type is output
D0 = _LC3_B1;
-- Node name is 'D1'
-- Equation name is 'D1', type is output
D1 = _LC5_B1;
-- Node name is 'D2'
-- Equation name is 'D2', type is output
D2 = _LC6_B6;
-- Node name is 'D3'
-- Equation name is 'D3', type is output
D3 = _LC1_B4;
-- Node name is 'D4'
-- Equation name is 'D4', type is output
D4 = _LC2_B8;
-- Node name is 'D5'
-- Equation name is 'D5', type is output
D5 = _LC4_B15;
-- Node name is 'D6'
-- Equation name is 'D6', type is output
D6 = _LC6_B15;
-- Node name is 'H'
-- Equation name is 'H', type is output
H = GND;
-- Node name is 'LG1'
-- Equation name is 'LG1', type is output
LG1 = _LC1_B9;
-- Node name is 'LG2'
-- Equation name is 'LG2', type is output
LG2 = _LC7_B9;
-- Node name is 'LG3'
-- Equation name is 'LG3', type is output
LG3 = _LC8_B9;
-- Node name is 'LG4'
-- Equation name is 'LG4', type is output
LG4 = _LC5_B13;
-- Node name is 'LR1'
-- Equation name is 'LR1', type is output
LR1 = !_LC5_B15;
-- Node name is 'LR2'
-- Equation name is 'LR2', type is output
LR2 = _LC6_B8;
-- Node name is 'LR3'
-- Equation name is 'LR3', type is output
LR3 = !_LC4_B12;
-- Node name is 'LR4'
-- Equation name is 'LR4', type is output
LR4 = _LC1_B15;
-- Node name is 'LY1'
-- Equation name is 'LY1', type is output
LY1 = _LC3_B8;
-- Node name is 'LY2'
-- Equation name is 'LY2', type is output
LY2 = _LC8_B6;
-- Node name is 'LY3'
-- Equation name is 'LY3', type is output
LY3 = _LC2_B9;
-- Node name is 'LY4'
-- Equation name is 'LY4', type is output
LY4 = _LC1_B16;
-- Node name is 'Y0'
-- Equation name is 'Y0', type is output
Y0 = !_LC4_B5;
-- Node name is 'Y1'
-- Equation name is 'Y1', type is output
Y1 = _LC3_B4;
-- Node name is 'Y2'
-- Equation name is 'Y2', type is output
Y2 = GND;
-- Node name is 'Y3'
-- Equation name is 'Y3', type is output
Y3 = GND;
-- Node name is 'Y4'
-- Equation name is 'Y4', type is output
Y4 = _LC8_B1;
-- Node name is 'Y5'
-- Equation name is 'Y5', type is output
Y5 = !_LC1_B1;
-- Node name is 'Y6'
-- Equation name is 'Y6', type is output
Y6 = GND;
-- Node name is 'Y7'
-- Equation name is 'Y7', type is output
Y7 = GND;
-- Node name is '|T10:1|dk:l_c|~177~1'
-- Equation name is '_LC1_B9', type is buried
-- synthesized logic cell
_LC1_B9 = LCELL( _EQ001);
_EQ001 = _LC3_B9 & _LC6_B8;
-- Node name is '|T10:1|dk:l_c|:177'
-- Equation name is '_LC8_B9', type is buried
_LC8_B9 = LCELL( _EQ002);
_EQ002 = _LC3_B9 & _LC6_B8;
-- Node name is '|T10:1|dk:l_c|:214'
-- Equation name is '_LC5_B6', type is buried
_LC5_B6 = LCELL( _EQ003);
_EQ003 = !_LC1_B6 & !_LC2_B6;
-- Node name is '|T10:1|dk:l_c|:220'
-- Equation name is '_LC3_B9', type is buried
_LC3_B9 = LCELL( _EQ004);
_EQ004 = !_LC1_B6 & !_LC2_B6
# clk & !_LC2_B6
# clk & !_LC1_B6
# !_LC4_B8;
-- Node name is '|T10:1|dk:l_c|~221~1'
-- Equation name is '_LC7_B9', type is buried
-- synthesized logic cell
_LC7_B9 = LCELL( _EQ005);
_EQ005 = _LC3_B9 & !_LC6_B8;
-- Node name is '|T10:1|dk:l_c|:221'
-- Equation name is '_LC5_B13', type is buried
_LC5_B13 = LCELL( _EQ006);
_EQ006 = _LC3_B9 & !_LC6_B8;
-- Node name is '|T10:1|dk:l_c|~261~1'
-- Equation name is '_LC2_B9', type is buried
-- synthesized logic cell
_LC2_B9 = LCELL( _EQ007);
_EQ007 = _LC1_B6 & _LC2_B6 & _LC4_B8 & _LC6_B8;
-- Node name is '|T10:1|dk:l_c|:261'
-- Equation name is '_LC3_B8', type is buried
_LC3_B8 = LCELL( _EQ008);
_EQ008 = _LC1_B6 & _LC2_B6 & _LC4_B8 & _LC6_B8;
-- Node name is '|T10:1|dk:l_c|~301~1'
-- Equation name is '_LC8_B6', type is buried
-- synthesized logic cell
_LC8_B6 = LCELL( _EQ009);
_EQ009 = _LC1_B6 & _LC2_B6 & _LC4_B8 & !_LC6_B8;
-- Node name is '|T10:1|dk:l_c|:301'
-- Equation name is '_LC1_B16', type is buried
_LC1_B16 = LCELL( _EQ010);
_EQ010 = _LC1_B6 & _LC2_B6 & _LC4_B8 & !_LC6_B8;
-- Node name is '|T10:1|sx:l_d|:321'
-- Equation name is '_LC6_B10', type is buried
_LC6_B10 = LCELL( _EQ011);
_EQ011 = !_LC1_B6 & !_LC2_B4 & !_LC2_B6 & _LC4_B8;
-- Node name is '|T10:1|sx:l_d|:357'
-- Equation name is '_LC3_B10', type is buried
!_LC3_B10 = _LC3_B10~NOT;
_LC3_B10~NOT = LCELL( _EQ012);
_EQ012 = !_LC2_B6
# !_LC2_B4
# _LC1_B6
# !_LC4_B8;
-- Node name is '|T10:1|sx:l_d|~384~1'
-- Equation name is '_LC8_B15', type is buried
-- synthesized logic cell
_LC8_B15 = LCELL( _EQ013);
_EQ013 = _LC1_B6 & !_LC2_B6 & _LC4_B8;
-- Node name is '|T10:1|sx:l_d|~384~2'
-- Equation name is '_LC2_B15', type is buried
-- synthesized logic cell
_LC2_B15 = LCELL( _EQ014);
_EQ014 = _LC2_B6
# !_LC1_B6 & !_LC4_B8
# !_LC1_B6 & _LC2_B4
# _LC1_B6 & _LC4_B8
# _LC2_B4 & _LC4_B8;
-- Node name is '|T10:1|sx:l_d|:393'
-- Equation name is '_LC1_B8', type is buried
!_LC1_B8 = _LC1_B8~NOT;
_LC1_B8~NOT = LCELL( _EQ015);
_EQ015 = !_LC4_B8
# !_LC1_B6
# !_LC2_B6
# _LC2_B4;
-- Node name is '|T10:1|sx:l_d|:405'
-- Equation name is '_LC8_B8', type is buried
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