dk.vhd

几个VHDL实现的源程序及其代码

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY dk IS
	PORT(
		cp : IN STD_LOGIC;
		sj : IN	STD_LOGIC_VECTOR(4 downto 1);
		lr,lg,ly : OUT	STD_LOGIC_VECTOR(4 downto 1));
END dk;
ARCHITECTURE a OF dk IS
SIGNAL ra,rb,ga,gb,ya,yb : STD_LOGIC;
BEGIN
ra <= sj(4);
rb <= not sj(4);
ga <= (not sj(4))and (sj(3) or (sj(2) and sj(1)) or ((sj(2) xor sj(1)) and cp));
gb <=      sj(4) and (sj(3) or (sj(2) and sj(1)) or ((sj(2) xor sj(1)) and cp));
ya <= (not sj(4))and (not(sj(3) or sj(2) or sj(1)));
yb <=      sj(4) and (not(sj(3) or sj(2) or sj(1)));
lr(1) <= ra;
lr(2) <= rb;
lr(3) <= ra;
lr(4) <= rb;
lg(1) <= ga;
lg(2) <= gb;
lg(3) <= ga;
lg(4) <= gb;
ly(1) <= ya;
ly(2) <= yb;
ly(3) <= ya;
ly(4) <= yb;
END a;